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The interface supports access widths that are a power of two bytes, most commonly one, two, four, or eight bytes, as specified in the
byteWidth argument to
Instances are not required to support all access widths for all addresses. They can either return an error if elements could not be read or written or they can return zero for reads, and ignore writes.
All accesses must be naturally aligned, or
Memory locations are read from lower addresses to higher addresses. Accessing memory does not stop on read or write errors.
count argument to
memory_write() is greater than one, instances can convert debug accesses covering multiple elements into burst accesses, if the bus supports it. Buses must break debug burst accesses into individual accesses transparently, for example when passing accesses to peripheral buses that do not support bursts. To reduce the function call overhead, clients should generally make the access count as large as possible.