5.7.7 Memory access attributes

The set of memory access attributes that are available depends on the target instance and the memory space within it. The supported attributes and their semantics are listed in the target instance documentation and are also provided by the attrib and attribDefaults members of MemorySpaceInfo.

However, there are typical classes of instances and memory spaces that expose the same set of attributes. The following tables list all possible memory attributes as a guideline for instance implementations.


There are no attributes for generic storage components like RAM, ROM, flash, and other backing storage.

The translation regimes that are implemented by the CPU should be exposed as memory spaces. All virtually-addressed regimes should be exposed, if applicable. In addition, a physical view of the memory should be exposed as a memory space, if applicable.

See 5.7.6 Canonical memory space number scheme for a list of canonical memory spaces. Each memory space has a different set of default values for these attributes, which often define the semantics of the memory space.

Table 5-5 attrib object for Arm CPU components in virtually-addressed regimes

Name Type Description
privileged Boolean Access is privileged.
instruction Boolean For reads, access is on the instruction side if True, or data side if False.
user NumberU64 User signaling (AXI4).

Table 5-6 attrib object for Arm CPU components in physically-addressed regimes

Name Type Description
nonSecure Boolean Access is non-secure if True, or secure if False.
type String Device or normal memory type. Must be one of the following:
  • "Device-nGnRnE" (strongly-ordered).
  • "Device-nGnRE" (device).
  • "Device-nGRE" (v8-specific).
  • "Device-GRE" (v8-specific).
  • "Normal" (innerCacheability, outerCacheability, and shareability define the attributes).
innerCacheability String Cacheability for the inner domain. Must be one of:
  • "NC" (Non-Cacheable).
  • "WT" (Write-Through).
  • "WB" (Write-Back).
This is only relevant for type=Normal and ignored for other types. These attributes are only used for routing the debug transaction. Debug accesses on caches have special semantics. For WT and WB there are no allocation hints for debug accesses as debug accesses never allocate. For more information, see 5.7.9 Reading and writing through caches and buffers.
outerCacheability String Cacheability for the outer domain. See innerCacheability.
shareability String Shareability. Must be one of:
  • "nsh" (Non-Shareable).
  • "ish" (Inner Shareable).
  • "osh" (Outer Shareable).

This is only relevant for type=Normal and is ignored for other types.


When both innerCacheability and outerCacheability are NC, shareability is ignored and is Outer Shareable.
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