5.7.6 Canonical memory space number scheme

All Arm® components implement the canonical memory space number scheme arm.com/memoryspaces.

It allows debuggers to programmatically select a specific translation regime. The semantics of some memory spaces depend on the Arm architecture version and even on the configuration of EL3.

The following ids are defined for the canonicalMsn member of MemorySpaceInfo:

Table 5-4 Canonical memory space number scheme arm.com/memoryspaces

canonicalMsn (NumberU64) Architecture and configuration Name Semantics and translation regime
0x1000 Armv8 EL3=AArch64 Secure Monitor Virtual memory as seen by code running at EL3. This is always secure. This is virtual memory as configured by TCR_EL3.
Armv7, Armv8, EL3=AArch32 Secure Monitor Virtual memory as seen by code running at PL0 or PL1 on the secure side. This is always secure. This is virtual memory as configured by TTBCR(secure).
Armv6, Armv7 Secure Virtual memory as configured by TTBCR(secure).
0x1001 Armv8 EL3=AArch64 Guest Virtual memory as seen by code running at EL0 or EL1. This can be secure or non-secure. This is virtual memory as configured by TCR_EL1/TTBCR(non-secure).

Note:

Although this is the non-secure bank of TTBCR, this does not make accesses non-secure in this configuration.
Armv7, Armv8, EL3=AArch32 Guest Virtual memory as seen by code running at PL0 or PL1 on the non-secure side. This is always non-secure. This is virtual memory as configured by TTBCR(non-secure).
Armv6, Armv7 Normal This is virtual memory as configured by TTBCR(non-secure).
0x1002 Armv7, Armv8 NS Hyp Virtual memory as seen by code running at EL2/PL2, for AArch64/AArch32. This is always non-secure. This is memory as configured by TCR_EL2/HTCR, for AArch64/AArch32.
0x1003 Armv5, Armv6, Armv7 Memory Virtual memory. Cores and other components that do not have TrustZone®.
0x1004 Armv7, Armv8 Hyp App Virtual memory as seen from EL0 (32 or 64) running under a hypervisor with HCR.TGE=1. This has stage1 implicitly disabled but is still translated by stage2.
0x1005 Armv8.1 Host Virtual memory as seen from EL0 (32 or 64) and EL2 (64) with HCR.E2H=1 and HCR.TGE=1. This has stage1 controlled by TCR_EL2 and implicitly disables stage2.
0x10ff All Current Virtual memory view of the current exception level, protection level, or mode. The translation regime used follows the current state of the CPU.
0x1100 Armv7, Armv8 IPA Intermediate physical memory view. Non-secure.
0x1200 Armv6, Armv7, Armv8 Physical Memory (Secure) Physical memory, secure world.
0x1201 Armv6, Armv7, Armv8 Physical Memory (Non Secure) Physical memory, non-secure world.
0x1202 Armv5, Armv6, Armv7 Physical Memory Physical memory. Cores and components that do not have TrustZone.

Note:

  • Entries in the Name column are for information only and are not binding. They reflect the names that are used by existing models. The purpose of the canonicalMsn is for clients to use it to find a memory space with specific semantics.
  • Armv8 instances support the AArch64 and AArch32 modes at runtime for the memory spaces with canonicalMsn = 0x1000, 0x1001, and 0x1002. These memory spaces should have the static properties of AArch64, with 64-bit wide virtual addresses.
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