Arm® Cortex®-M55 Processor Devices Generic User Guide

Revision r0p1

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1 Introduction, Reference Material
1.1 About this document
1.1.1 Typographic conventions
1.2 About the Cortex®-M55 processor and core peripherals
1.2.1 System-level interface
1.2.2 Security Extension
1.2.3 Integrated configurable debug
1.2.4 Processor features and benefits summary
1.2.5 Processor core peripherals
1.3 Arm®v8.1‑M enablement content
2 The Cortex®-M55 Processor, Reference Material
2.1 Programmer's model
2.1.1 Processor modes and privilege levels for software execution
2.1.2 Security states
2.1.3 Core registers
2.1.4 Exceptions and interrupts
2.1.5 Data types and data memory accesses
2.1.6 The Cortex Microcontroller Software Interface Standard
2.2 Memory model
2.2.1 Processor memory map
2.2.2 Memory regions, types, and attributes
2.2.3 Device memory
2.2.4 Secure memory system and memory partitioning
2.2.5 Behavior of memory accesses
2.2.6 Memory endianness
2.2.7 Synchronization primitives
2.2.8 Programming hints for the synchronization primitives
2.3 Exception model
2.3.1 Exception states
2.3.2 Exception types
2.3.3 Exception handlers
2.3.4 Vector table
2.3.5 Exception priorities
2.3.6 Interrupt priority grouping
2.3.7 Exception handling
2.4 Security state switches
2.5 Fault handling
2.5.1 Fault types reference table
2.5.2 Fault escalation to HardFault
2.5.3 Fault status registers and fault address registers
2.5.4 Lockup
2.6 Power management
2.6.1 Entering sleep mode
2.6.2 Wakeup from sleep mode
2.6.3 The Wakeup Interrupt Controllers
2.6.4 The external event input
2.6.5 Power management programming hints
2.7 Arm®v8.1‑M MVE overview
3 The Cortex®-M55 Instruction Set, Reference Material
3.1 Cortex®-M55 instructions
3.1.1 Binary compatibility with other Cortex processors
3.2 CMSIS functions
3.2.1 List of CMSIS functions to generate some processor instructions
3.2.2 CMSE
3.2.3 CMSIS functions to access the special registers
3.2.4 CMSIS functions to access the Non-secure special registers
3.3 Operands
3.4 Restrictions when using PC or SP
3.5 Flexible second operand
3.5.1 Constant
3.5.2 Register with optional shift
3.6 Right shift operations
3.6.1 ASR
3.6.2 ASRL
3.6.3 LSR
3.6.4 LSRL
3.6.5 SRSHR
3.6.6 SRSHRL
3.6.7 SQRSHR
3.6.9 URSHR
3.6.10 URSHRL
3.7 Left shift operations
3.7.1 LSL
3.7.2 LSLL
3.7.3 SQSHL
3.7.4 SQSHLL
3.7.5 UQSHL
3.7.6 UQSHLL
3.7.7 UQRSHL
3.8 Rotate shift operations
3.8.1 ROR
3.8.2 RORS
3.8.3 RRX
3.8.4 RRXS
3.9 Address alignment
3.10 PCrelative expressions
3.11 Conditional execution
3.11.1 The condition flags
3.11.2 Condition code suffixes
3.11.3 Predication
3.12 Instruction width selection
3.13 General data processing instructions
3.13.1 List of data processing instructions
3.13.2 ADD, ADC, SUB, SBC, and RSB
3.13.3 AND, ORR, EOR, BIC, and ORN
3.13.4 ASR, LSL, LSR, ROR, and RRX
3.13.5 CLZ
3.13.6 CMP and CMN
3.13.7 MOV and MVN
3.13.8 MOVT
3.13.9 REV, REV16, REVSH, and RBIT
3.13.10 SADD16 and SADD8
3.13.11 SASX and SSAX
3.13.12 SEL
3.13.13 SHADD16 and SHADD8
3.13.14 SHASX and SHSAX
3.13.15 SHSUB16 and SHSUB8
3.13.16 SSUB16 and SSUB8
3.13.17 TST and TEQ
3.13.18 UADD16 and UADD8
3.13.19 UASX and USAX
3.13.20 UHADD16 and UHADD8
3.13.21 UHASX and UHSAX
3.13.22 UHSUB16 and UHSUB8
3.13.23 USAD8
3.13.24 USADA8
3.13.25 USUB16 and USUB8
3.14 Coprocessor instructions
3.14.1 List of coprocessor instructions
3.14.2 Coprocessor intrinsics
3.14.3 CDP and CDP2
3.14.4 MCR and MCR2
3.14.5 MCRR and MCRR2
3.14.6 MRC and MRC2
3.14.7 MRRC and MRRC2
3.15 Multiply and divide instructions
3.15.1 List of multiply and divide instructions
3.15.2 MUL, MLA, and MLS
3.15.3 SDIV and UDIV
3.15.5 SMLAD and SMLADX
3.15.7 SMLSD and SMLSLD
3.15.8 SMMLA and SMMLS
3.15.9 SMMUL
3.15.10 SMUAD and SMUSD
3.15.11 SMUL and SMULW
3.16 Saturating instructions
3.16.1 List of saturating instructions
3.16.2 SSAT and USAT
3.16.3 SSAT16 and USAT16
3.16.4 QADD and QSUB
3.16.5 QASX and QSAX
3.16.6 QDADD and QDSUB
3.16.7 UQASX and UQSAX
3.16.8 UQADD and UQSUB
3.17 Packing and unpacking instructions
3.17.1 List of packing and unpacking instructions
3.17.2 PKHBT and PKHTB
3.17.3 SXTA and UXTA
3.17.4 SXT and UXT
3.18 Bit field instructions
3.18.1 List of bit field instructions
3.18.2 BFC and BFI
3.18.3 SBFX and UBFX
3.19 Branch and control instructions
3.19.1 List of branch and control instructions
3.19.2 B, BL, BX, and BLX
3.19.3 BXNS and BLXNS
3.19.4 CBZ and CBNZ
3.19.5 IT
3.19.6 TBB and TBH
3.20 Floating-point instructions
3.20.1 List of floating-point instructions
3.20.4 VABS
3.20.5 VADD
3.20.6 VCMP and VCMPE
3.20.7 VCVT and VCVTR between floating-point and integer
3.20.8 VCVT between floating-point and fixed-point
3.20.9 VDIV
3.20.10 VFMA and VFMS
3.20.11 VFNMA and VFNMS
3.20.12 VLDM
3.20.13 VLDR
3.20.14 VLLDM
3.20.15 VLSTM
3.20.16 VMLA and VMLS
3.20.17 VMOV Immediate
3.20.18 VMOV Register
3.20.19 VMOV scalar to core register
3.20.20 VMOV core register to single-precision
3.20.21 VMOV two core registers to two single-precision registers
3.20.22 VMOV two core registers and a double-precision register
3.20.23 VMOV core register to scalar
3.20.24 VMRS
3.20.25 VMSR
3.20.26 VMUL
3.20.27 VNEG
3.20.28 VNMLA, VNMLS and VNMUL
3.20.29 VPOP
3.20.30 VPUSH
3.20.31 VSQRT
3.20.32 VSTM
3.20.33 VSTR
3.20.34 VSUB
3.20.35 VSEL
3.20.37 VCVTB and VCVTT
3.20.38 VMAXNM and VMINNM
3.20.39 VRINTR and VRINTX
3.21 Arm®v8.1‑M shift, saturate, and reverse operations instructions
3.21.1 List of Arm®v8.1‑M shift, saturate, and reverse operations instructions
3.21.2 ASRL (immediate)
3.21.3 ASRL (register)
3.21.4 LSLL (immediate)
3.21.5 LSLL (register)
3.21.6 LSRL (immediate)
3.21.7 SQRSHR (register)
3.21.8 SQRSHRL (register)
3.21.9 SQSHL (immediate)
3.21.10 SQSHLL (immediate)
3.21.11 SRSHR (immediate)
3.21.12 SRSHRL (immediate)
3.21.13 UQRSHL (register)
3.21.14 UQRSHLL (register)
3.21.15 UQSHL (immediate)
3.21.16 UQSHLL (immediate)
3.21.17 URSHR (immediate)
3.21.18 URSHRL (immediate)
3.21.19 VBRSR
3.21.20 VMOVL
3.21.21 VMOVN
3.21.22 VQMOVN
3.21.23 VQMOVUN
3.21.24 VQRSHL
3.21.25 VQRSHRN
3.21.26 VQRSHRUN
3.21.28 VQSHRN
3.21.29 VQSHRUN
3.21.30 VRSHL
3.21.31 VRSHR
3.21.32 VRSHRN
3.21.33 VSHL
3.21.34 VSHLC
3.21.35 VSHLL
3.21.36 VSHR
3.21.37 VSHRN
3.21.38 VSLI
3.21.39 VSRI
3.22 Arm®v8.1‑M branch and loop instructions
3.22.1 List of Arm®v8.1‑M branch and loop instructions
3.22.3 LCTP
3.22.4 LE, LETP
3.23 Arm®v8.1‑M comparison and vector predication operations instructions
3.23.1 List of Arm®v8.1‑M comparison and vector predication operations instructions
3.23.2 CINC
3.23.3 CINV
3.23.4 CNEG
3.23.5 CSEL
3.23.6 CSET
3.23.7 CSETM
3.23.8 CSINC
3.23.9 CSINV
3.23.10 CSNEG
3.23.11 VCMP
3.23.12 VCMP (floating-point)
3.23.13 VCTP
3.23.14 VMAX, VMAXA
3.23.15 VMAXNM, VMAXNMA (floating-point)
3.23.16 VMAXNMV, VMAXNMAV (floating-point)
3.23.18 VMIN, VMINA
3.23.19 VMINNM, VMINNMA (floating-point)
3.23.20 VMINNMV, VMINNMAV (floating-point)
3.23.22 VPNOT
3.23.23 VPST
3.23.24 VPT
3.23.25 VPT (floating-point)
3.24 Arm®v8.1‑M vector load and store operations instructions
3.24.1 List of Arm®v8.1‑M vector load and store operations instructions
3.24.2 VLD2
3.24.3 VLD4
3.24.4 VLDR (System Register)
3.24.6 VLDRB, VLDRH, VLDRW, VLDRD (vector)
3.24.7 VST2
3.24.8 VST4
3.24.9 VSTR (System Register)
3.24.11 VSTRB, VSTRH, VSTRW, VSTRD (vector)
3.25 Arm®v8.1‑M vector move operation instructions
3.25.1 List of Arm®v8.1‑M vector move operation instructions
3.25.2 VMOV (two 32 bit vector lanes to two general-purpose registers)
3.25.3 VMOV (two general-purpose registers to two 32 bit vector lanes)
3.26 Arm®v8.1‑M RAS instruction
3.26.1 ESB
3.27 Arm®v8.1‑M vector floating-point conversion and rounding operation instructions
3.27.1 List of Arm®v8.1‑M vector floating-point conversion and rounding operation instructions
3.27.2 VCVT (between floating-point and fixed-point)
3.27.3 VCVT (between floating-point and integer)
3.27.4 VCVT (between single and half-precision floating-point)
3.27.5 VCVT (from floating-point to integer)
3.28 Arm®v8.1‑M security instructions
3.28.1 List of Arm®v8.1‑M security instructions
3.28.2 CLRM
3.28.3 VSCCLRM
3.29 Arm®v8.1‑M vector arithmetic instructions
3.29.1 List of Arm®v8.1‑M vector arithmetic instructions
3.29.2 VABAV
3.29.3 VABD
3.29.4 VABD (floating-point)
3.29.5 VABS
3.29.6 VABS (floating-point)
3.29.7 VADC
3.29.8 VADD
3.29.9 VADD (floating-point)
3.29.10 VADDLV
3.29.11 VADDV
3.29.12 VCADD
3.29.13 VCADD (floating-point)
3.29.14 VCLS
3.29.15 VCLZ
3.29.16 VCMLA (floating-point)
3.29.17 VCMUL (floating-point)
3.29.19 VDUP
3.29.20 VFMA (vector by scalar plus vector, floating-point)
3.29.21 VFMA, VFMS (floating-point)
3.29.22 VFMAS (vector by vector plus scalar, floating-point)
3.29.23 VHADD
3.29.24 VHCADD
3.29.25 VHSUB
3.29.27 VMLA (vector by scalar plus vector)
3.29.28 VMLADAV
3.29.29 VMLALDAV
3.29.30 VMLALV
3.29.31 VMLAS (vector by vector plus scalar)
3.29.32 VMLAV
3.29.33 VMLSDAV
3.29.34 VMLSLDAV
3.29.35 VMUL
3.29.36 VMUL (floating-point)
3.29.38 VMULL (integer)
3.29.39 VMULL (polynomial)
3.29.40 VNEG
3.29.41 VNEG (floating-point)
3.29.42 VQABS
3.29.43 VQADD
3.29.45 VQDMLAH, VQRDMLAH (vector by scalar plus vector)
3.29.46 VQDMLASH, VQRDMLASH (vector by vector plus scalar)
3.29.49 VQDMULL
3.29.50 VQNEG
3.29.51 VQSUB
3.29.52 VRHADD
3.29.53 VRINT (floating-point)
3.29.55 VRMLALVH
3.29.57 VSBC
3.29.58 VSUB
3.29.59 VSUB (floating-point)
3.30 Arm®v8.1‑M vector bitwise operations instructions
3.30.1 List of Arm®v8.1‑M vector bitwise operations instructions
3.30.2 VAND
3.30.3 VAND (immediate)
3.30.4 VBIC (immediate)
3.30.5 VBIC (register)
3.30.6 VEOR
3.30.7 VMOV (immediate)
3.30.8 VMOV (register)
3.30.9 VMOV (general-purpose register to vector lane)
3.30.10 VMOV (vector lane to general-purpose register)
3.30.11 VMVN (immediate)
3.30.12 VMVN (register)
3.30.13 VORN
3.30.14 VORN (immediate)
3.30.15 VORR
3.30.16 VORR (immediate)
3.30.17 VPSEL
3.30.18 VREV16
3.30.19 VREV32
3.30.20 VREV64
3.31 Miscellaneous instructions
3.31.1 List of miscellaneous instructions
3.31.2 BKPT
3.31.3 CPS
3.31.4 CPY
3.31.5 DMB
3.31.6 DSB
3.31.7 ISB
3.31.8 MRS
3.31.9 MSR
3.31.10 NOP
3.31.11 SEV
3.31.12 SG
3.31.13 SVC
3.31.14 TT, TTT, TTA, and TTAT
3.31.15 UDF
3.31.16 WFE
3.31.17 WFI
3.31.18 YIELD
3.32 Memory access instructions
3.32.1 List of memory access instructions
3.32.2 ADR
3.32.3 LDR and STR, immediate offset
3.32.4 LDR and STR, register offset
3.32.5 LDR and STR, unprivileged
3.32.6 LDR, PC‑relative
3.32.7 LDM and STM
3.32.8 PLD
3.32.9 PUSH and POP
3.32.10 LDA and STL
3.32.11 LDREX and STREX
3.32.12 LDAEX and STLEX
3.32.13 CLREX
4 Cortex®-M55 Processor-level components and system registers , Reference Material
4.1 The Cortex®-M55 system registers
4.2 Nested Vectored Interrupt Controller
4.2.1 Accessing the NVIC registers using CMSIS
4.2.2 Interrupt Set Enable Registers
4.2.3 Interrupt Clear Enable Registers
4.2.4 Interrupt Set Pending Registers
4.2.5 Interrupt Active Bit Registers
4.2.6 Interrupt Target Non-secure Registers
4.2.7 Interrupt Priority Registers
4.2.8 Interrupt Clear Pending Registers
4.2.9 Software Trigger Interrupt Register
4.2.10 Level-sensitive and pulse interrupts
4.3 System Control and Implementation Control Block
4.3.1 System control block registers summary
4.3.2 Auxiliary Fault Status Register
4.3.3 Auxiliary Feature Register 0
4.3.4 Application Interrupt and Reset Control Register
4.3.5 Bus Fault Address Register
4.3.6 Cache Level ID Register
4.3.7 Cache Size Selection Register
4.3.8 Cache Type Register
4.3.9 Current Cache Size ID Register
4.3.10 CPUID Base Register
4.3.11 Configuration and Control Register
4.3.12 Configurable Fault Status Register
4.3.13 Coprocessor Access Control Register
4.3.14 Processor Feature Register 0
4.3.15 Processor Feature Register 1
4.3.16 Debug Fault Status Register
4.3.17 HardFault Status Register
4.3.18 Interrupt Control and State Register
4.3.19 Instruction Set Attribute Register 0
4.3.20 Instruction Set Attribute Register 1
4.3.21 Instruction Set Attribute Register 2
4.3.22 Instruction Set Attribute Register 3
4.3.23 Instruction Set Attribute Register 4
4.3.24 Instruction Set Attribute Register 5
4.3.25 MemManage Fault Address Register
4.3.26 Memory Model Feature Register 0
4.3.27 Memory Model Feature Register 1
4.3.28 Memory Model Feature Register 2
4.3.29 Memory Model Feature Register 3
4.3.30 Non-secure Access Control Register
4.3.31 System Control Register
4.3.32 System Handler Control and State Register
4.3.33 System Handler Priority Registers
4.3.34 Revision ID Register, REVIDR
4.3.35 Vector Table Offset Register
4.3.36 System Control Block design hints and tips
4.3.37 Implementation control block register summary
4.3.38 Auxiliary Control Register
4.3.39 Interrupt Controller Type Register
4.3.40 Coprocessor Power Control Register
4.3.41 NVIC usage hints and tips
4.4 System timer, SysTick
4.4.1 SysTick Control and Status Register
4.4.2 SysTick Reload Value Register
4.4.3 SysTick Current Value Register
4.4.4 SysTick Calibration Value Register
4.4.5 SysTick usage hints and tips
4.5 Cache maintenance operations
4.5.1 Instruction Cache Invalidate All to PoU, ICIALLU
4.5.2 Instruction Cache line Invalidate by Address to PoU, ICIMVAU
4.5.3 Data Cache line Invalidate by Address to PoC, DCIMVAC
4.5.4 Data Cache line Invalidate by Set/Way, DCISW
4.5.5 Data cache clean by address to the PoU, DCCMVAU
4.5.6 Data cache line clean by address to the PoC, DCCMVAC
4.5.7 Data Cache Clean line by Set/Way, DCCSW
4.5.8 Data Cache Clean and Invalidate by Address to the PoC, DCCIMVAC
4.5.9 Data Cache Clean and Invalidate by Set/Way, DCCISW
4.5.10 Branch Predictor Invalidate All, BPIALL
4.5.11 Accessing the NVIC cache maintenance operations using CMSIS
4.5.12 Initializing the instruction and data cache
4.5.13 Enabling the instruction and data cache
4.5.14 Powering down the caches
4.5.15 Powering up the caches
4.5.16 Enabling the branch cache
4.5.17 Fault handling considerations
4.5.18 Cache maintenance design
4.6 Memory Authentication
4.6.1 Security Attribution Unit
4.6.2 Memory Protection Unit
4.6.3 Implementation Defined Attribution Unit
4.7 Implementation defined register summary
4.8 Implementation defined memory system control registers
4.8.1 Direct cache access registers
4.8.2 Memory System Control Register, MSCR
4.8.3 P-AHB Control Register, PAHBCR
4.8.4 Prefetcher Control Register, PFCR
4.8.5 TCM Control Registers, ITCMCR and DTCMCR
4.8.6 TCM security gate registers
4.9 Implementation defined power mode control
4.9.1 Core Power Domain Low Power State Register, CPDLPSTATE
4.9.2 Debug Power Domain Low Power State Register, DPDLPSTATE
4.10 Implementation defined error banking registers
4.10.1 Instruction Cache Error Bank Register 0-1, IEBR0 and IEBR1
4.10.2 Data Cache Error Bank Register 0-1, DEBR0 and DEBR1
4.10.3 TCM Error Bank Register 0-1, TEBR0 and TEBR1
4.11 Processor configuration information implementation defined registers
4.11.1 Processor configuration information selection register, CFGINFOSEL
4.11.2 Processor configuration information read data register, CFGINFORD
4.12 Floating-point and MVE support
4.12.1 Floating-point and MVE register summary
4.12.2 FPDSCR and FPSCR register reset values
4.12.3 Floating-point Context Control Register, FPCCR
4.12.4 Floating-point Context Address Register, FPCAR
4.12.5 Floating-point Status Control Register, FPSCR
4.12.6 Floating-point Default Status Control Register
4.12.7 Media and VFP Feature Register 0
4.12.8 Media and VFP Feature Register 1
4.12.9 Media and VFP Feature Register 2
4.13 EWIC interrupt status access registers
4.13.1 Event Set Pending Register
4.13.2 Wake-up Event Mask Registers
5 Reliability, Availability, and Serviceability Extension support
5.1 Cortex®-M55 processor implementation of Arm®v8.1‑M RAS
5.1.1 Cortex®-M55 RAS events
5.2 ECC memory protection behavior
5.2.1 ECC schemes and error type terminology
5.2.2 Enabling ECC
5.2.3 Error detection and processing
5.2.4 Error reporting
5.2.5 Address decoder and white noise protection
5.3 Interface protection behavior
5.4 M-AXI read access poisoning
5.5 RAS memory barriers
5.6 Arm®v8.1‑M RAS Extension registers
5.6.1 Error Record Feature Register, ERRFR0
5.6.2 Error Record Primary Status Register, ERRSTATUS0
5.6.3 Error Record Address Registers, ERRADDR0 and ERRADDR20
5.6.4 Error Record Miscellaneous Register 10, ERRMISC10
5.6.5 Fault Group Status Register, ERRGSR0
5.6.6 Error Record Device ID Register, ERRDEVID
5.6.7 Fault Status Register, RFSR
6 Performance Monitoring Unit Extension support
6.1 PMU features
6.2 PMU events
6.3 PMU register summary
6.4 Performance Monitoring Unit Event Counter Register, PMU_EVCNTR0-7
6.5 Performance Monitoring Unit Cycle Counter Register, PMU_CCNTR
6.6 Performance Monitoring Unit Event Type and Filter Register, PMU_EVTYPER0-7
6.7 Performance Monitoring Unit Count Enable Set Register, PMU_CNTENSET
6.8 Performance Monitoring Unit Count Enable Clear Register, PMU_CNTENCLR
6.9 Performance Monitoring Unit Interrupt Enable Set Register, PMU_INTENSET
6.10 Performance Monitoring Unit Interrupt Enable Clear Register, PMU_INTENCLR
6.11 Performance Monitoring Unit Overflow Flag Status Clear Register, PMU_OVSCLR
6.12 Performance Monitoring Unit Overflow Flag Status Set Register, PMU_OVSSET
6.13 Performance Monitoring Unit Software Increment Register, PMU_SWINC
6.14 Performance Monitoring Unit Type Register, PMU_TYPE
6.15 Performance Monitoring Unit Control Register, PMU_CTRL
6.16 Performance Monitoring Unit Authentication Status Register, PMU_AUTHSTATUS
6.17 Performance Monitoring Unit Device Architecture Register, PMU_DEVARCH
6.18 Performance Monitoring Unit Device Type Register, PMU_DEVTYPE
6.19 Performance Monitoring Unit Peripheral Identification Register 0, PMU_PIDR0
6.20 Performance Monitoring Unit Peripheral Identification Register 1, PMU_PIDR1
6.21 Performance Monitoring Unit Peripheral Identification Register 2, PMU_PIDR2
6.22 Performance Monitoring Unit Peripheral Identification Register 3, PMU_PIDR3
6.23 Performance Monitoring Unit Peripheral Identification Register 4, PMU_PIDR4
6.24 Performance Monitoring Unit Component Identification Register 0, PMU_CIDR0
6.25 Performance Monitoring Unit Component Identification Register 1, PMU_CIDR1
6.26 Performance Monitoring Unit Component Identification Register 2, PMU_CIDR2
6.27 Performance Monitoring Unit Component Identification Register 3, PMU_CIDR3
A External Wakeup Interrupt Controller
A.1 EWIC features
A.2 EWIC register summary
A.3 EWIC Control Register
A.4 EWIC Automatic Sequence Control Register
A.5 EWIC Clear Mask Register
A.6 EWIC Event Number ID Register
A.7 EWIC Mask Registers
A.8 EWIC Pend Event Registers
A.9 EWIC Pend Summary Register
A.10 EWIC CoreSight™ register summary
A.11 EWIC Integration Mode Control Register
A.12 EWIC Claim Tag Set Register
A.13 EWIC Claim Tag Clear Register
A.14 EWIC Device Affinity Register 0
A.15 EWIC Device Affinity Register 1
A.16 EWIC Software Lock Access Register
A.17 EWIC Software Lock Status Register
A.18 EWIC Authentication Status Register
A.19 EWIC Device Architecture Register
A.20 EWIC Device Configuration Register 2
A.21 EWIC Device Configuration Register 1
A.22 EWIC Device Configuration Register
A.23 EWIC Device Type Identifier Register, EWIC_DEVTYPE
A.24 Peripheral Identification Register 4, EWIC_PIDR4
A.25 Peripheral Identification Register 5, EWIC_PIDR5
A.26 Peripheral Identification Register 6, EWIC_PIDR6
A.27 Peripheral Identification Register 7, EWIC_PIDR7
A.28 Peripheral Identification Register 0, EWIC_PIDR0
A.29 Peripheral Identification Register 1, EWIC_PIDR1
A.30 Peripheral Identification Register 2, EWIC_PIDR2
A.31 Peripheral Identification Register 3, EWIC_PIDR3
A.32 Component Identification Register 0, EWIC_ CIDR0
A.33 Component Identification Register 1, EWIC_ CIDR1
A.34 Component Identification Register 2, EWIC_ CIDR2
A.35 Component Identification Register 3, EWIC_ CIDR3
B Revisions
B.1 Revisions

List of Figures

1 Key to timing diagram conventions
1-1 Cortex-M55 processor implementation without the Security Extension
1-2 Cortex-M55 processor implementation with the Security Extension
2-1 Core registers without the Security Extension
2-2 Core registers with the Security Extension
2-3 SP register bit assignments
2-4 XPSR bit assignments
2-5 APSR bit assignments
2-6 IPSR bit assignments if 0-479 interrupts are implemented
2-7 CONTROL bit assignments
2-8 CONTROL bit assignments
2-9 VPR bit assignments
2-10 Vector table without the Security Extension
2-11 Vector table with the Security Extension
2-12 Stack frame when an interrupt or an exception is preserved on the stack with or without floating-point state
2-13 Stack frame extended to save additional context when the Security Extension is implemented
2-14 Extended exception stack frame
2-15 Security state transitions
3-1 ASR #4
3-2 ASRL #4
3-3 LSR #4
3-4 LSRL #4
3-5 SRSHR #4
3-6 SRSHRL #4
3-7 LSL #4
3-8 LSLL #4
3-9 ROR #3
3-10 RRX
4-1 AFSR bit assignments
4-2 AIRCR bit assignments
4-3 BFAR bit assignments
4-4 CLIDR bit assignments
4-5 CSSELR bit assignments
4-6 CTR bit assignments
4-7 CCSIDR bit assignments
4-8 CPUID bit assignments
4-9 UFSR bit assignments
4-10 MMFSR bit assignments
4-11 CPACR bit assignments
4-12 ID_PFR0 bit assignments
4-13 ID_PFR1 bit assignments
4-14 DFSR bit assignments
4-15 ID_ISAR0 bit assignments
4-16 ID_ISAR1 bit assignments
4-17 ID_ISAR2 bit assignments
4-18 ID_ISAR3 bit assignments
4-19 ID_ISAR4 bit assignments
4-20 MMFAR bit assignments
4-21 ID_MMFR0 bit assignments
4-22 ID_MMFR2 bit assignments
4-23 ID_MMFR3 bit assignments
4-24 NSACR bit assignments
4-25 SCR bit assignments
4-26 SHCSR bit assignments
4-27 SHPR1 bit assignments
4-28 SHPR2 bit assignments
4-29 SHPR3 bit assignments
4-30 REVIDR bit assignments
4-31 VTOR bit assignments
4-32 ACTLR bit assignments
4-33 ICTR bit assignments
4-34 CPPWR bit assignments
4-35 SYST_CALIB_S bit assignments
4-36 SYST_CALIB_NS bit assignments
4-37 SYST_CALIB bit assignments
4-38 ICIALLU bit assignments
4-39 ICIMVAU bit assignments
4-40 DCIMVAC bit assignments
4-41 DCISW bit assignments
4-42 DCCMVAU bit assignments
4-43 DCCMVAC bit assignments
4-44 DCCSW bit assignments
4-45 DCCIMVAC bit assignments
4-46 DCCISW bit assignments
4-47 BPIALL bit assignments
4-48 SAU_CTRL bit assignments
4-49 SAU_TYPE bit assignments
4-50 SAU_RNR bit assignments
4-51 SAU_RBAR bit assignments
4-52 SAU_RLAR bit assignments
4-53 SFSR bit assignments
4-54 SFAR bit assignments
4-55 MPU_RNR bit assignments
4-56 MPU_RBAR bit assignments
4-57 MPU_RLAR bit assignments
4-58 MPU_MAIR0 bit assignments
4-59 DCAICLR bit assignments
4-60 DCADCLR bit assignments
4-61 DCAICRR bit assignments when reading the instruction cache tag RAM
4-62 DCADCRR bit assignments when reading the data cache tag RAM
4-63 DCAICRR and DCADCRR bit assignments when reading the instruction or data cache data RAM
4-64 MSCR bit assignments
4-65 PAHBCR bit assignments
4-66 PFCR bit assignments
4-67 ITCMCR and DTCMCR bit assignments
4-68 ITGU_CTRL and DTGU_CTRL bit assignments
4-69 ITGU_CFG and DTGU_CFG bit assignments
4-70 ITGU_LUTn and DTGU_LUTn bit assignments
4-71 CPDLPSTATE bit assignments
4-72 DPDLPSTATE bit assignments
4-73 IEBR0 and IEBR1 bit assignments
4-74 DEBR0 and DEBR1 bit assignments
4-75 TEBR0 and TEBR1 bit assignments
4-76 TEBRDATA0 and TEBRDATA1 bit assignments
4-77 CFGINFOSEL bit assignments
4-78 CFGINFOSEL bit assignments showing CFGMEMALIAS
4-79 CFGINFOSEL bit assignments showing IRQTIER when n=1
4-80 CFGINFORD bit assignments
4-81 CFGINFORD bit assignments showing CFGMEMALIAS
4-82 CFGINFORD bit assignments showing IRQTIER when n=1
4-83 MVFR0 bit assignments
4-84 MVFR1 bit assignments
4-85 MVFR2 bit assignments
4-86 EVENTSPR bit assignments
4-87 EVENTMASKA bit assignments
4-88 EVENTMASKn, where 0≤n≤15, bit assignments.
5-1 Error processing prioritization
5-2 ERRFR0 bit assignments
5-3 ERRSTATUS0 bit assignments
5-4 ERRADDR0 bit assignments
5-5 ERRADDR20 bit assignments
5-6 ERRMISC10 bit assignments
5-7 ERRGSR0 bit assignments
5-8 ERRDEVID bit assignments
5-9 RFSR bit assignments
A-1 EWIC_CR bit assignments
A-2 EWIC_ASCR bit assignments
A-3 EWIC_NUMID bit assignments
A-4 EWIC_MASKA bit assignments
A-5 EWIC_MASKn, where n=0-14 bit assignments
A-6 EWIC_PENDA bit assignments
A-7 EWIC_PENDn, where n=0-14 bit assignments
A-8 EWIC_PSR bit assignments
A-9 EWIC_DEVARCH bit assignments
A-10 EWIC_AUTHSTATUS bit assignments
A-11 EWIC_PIDR4 bit assignments
A-12 EWIC_PIDR5 bit assignments
A-13 EWIC_PIDR6 bit assignments
A-14 EWIC_PIDR7 bit assignments
A-15 EWIC_PIDR0 bit assignments
A-16 EWIC_PIDR1 bit assignments
A-17 EWIC_PIDR2 bit assignments
A-18 CTI_PIDR3 bit assignments
A-19 EWIC_CIDR0 bit assignments
A-20 EWIC_CIDR1 bit assignments
A-21 EWIC_CIDR2 bit assignments
A-22 EWIC_CIDR3 bit assignments

List of Tables

2-1 Core register set summary without the Security Extension
2-2 Core register set summary with the Security Extension
2-3 Stack pointer register without the Security Extension
2-4 Stack pointer register with the Security Extension
2-5 SP register bit assignments
2-6 Stack limit registers without the Security Extension
2-7 Stack limit registers with the Security Extension
2-8 MSPLIM and PSPLIM register bit assignments
2-9 XPSR register combinations
2-10 APSR bit assignments
2-11 IPSR bit assignments
2-12 EPSR bit assignments
2-13 RETPSR bit assignments
2-14 PRIMASK register bit assignments
2-15 FAULTMASK register bit assignments
2-16 BASEPRI register bit assignments
2-17 CONTROL register bit assignments
2-18 CONTROL register bit assignments
2-19 VPR bit assignments
2-20 Default memory map
2-21 Memory access behavior
2-22 Memory region shareability and cache policies
2-23 CMSIS functions for exclusive access instructions
2-24 Properties of the different exception types with the Security Extension
2-25 Properties of the different exception type without the Security Extensions
2-26 Extended priority
2-27 Exception return behavior, EXC_RETURN bit field description
2-28 Exception return behavior, EXC_RETURN bit field description
2-29 Security state transitions
2-30 Fault types and fault status registers
2-31 Fault status and fault address registers
3-1 Instruction set summary
3-2 CMSIS functions to generate some Cortex-M55 processor instructions
3-3 CMSIS functions to access the special registers
3-4 CMSIS intrinsic functions to access the Non-secure special registers
3-5 Condition code suffixes
3-6 Data processing instructions
3-7 Coprocessor instructions
3-8 Multiply and divide instructions
3-9 Saturating instructions
3-10 Packing and unpacking instructions
3-11 Bit field instructions
3-12 Branch and control instructions
3-13 Branch ranges
3-14 Floating-point instructions
3-15 Armv8.1‑M shift, saturate, and reverse operations instructions
3-16 Armv8.1‑M branch and loop instructions
3-17 Armv8.1‑M comparison and vector predication operations instructions
3-18 Armv8.1‑M vector load and store operations instructions
3-19 Armv8.1‑M vector move operation instructions
3-20 Armv8.1‑M vector floating-point conversion and rounding operation instructions
3-21 Armv8.1‑M security instructions
3-22 Armv8.1‑M arithmetic instructions
3-23 Armv8.1‑M bitwise operations instructions
3-24 Miscellaneous instructions
3-25 Security state and access permissions in the destination register
3-26 Memory access instructions
3-27 Offset ranges
3-28 Offset ranges
4-1 NVIC registers summary
4-2 CMSIS access NVIC functions
4-3 NVIC_ISERn bit assignments
4-4 NVIC_ICERn bit assignments
4-5 NVIC_ISPRn bit assignments
4-6 NVIC_IABRn bit assignments
4-7 NVIC_ITNSn bit assignments
4-8 NVIC_IPRn bit assignments
4-9 NVIC_ICPRn bit assignments
4-10 STIR bit assignments
4-11 SCB register summary
4-12 AFSR bit assignments
4-13 AIRCR bit assignments without the Security Extension
4-14 AIRCR bit assignments with the Security Extension
4-15 Priority grouping
4-16 BFAR bit assignments
4-17 CLIDR bit assignments
4-18 CSSELR bit assignments
4-19 CTR bit assignments
4-20 CCSIDR bit assignments
4-21 CPUID bit assignments
4-22 CCR bit assignments without the Security Extension
4-23 CCR bit assignments with the Security Extension
4-24 CFSR register bit assignments
4-25 UFSR bit assignments
4-26 BFSR bit assignments
4-27 MMFSR bit assignments
4-28 CPACR bit assignments
4-29 ID_PFR0 bit assignments
4-30 ID_PFR1 bit assignments
4-31 DFSR bit assignments
4-32 HFSR bit assignments
4-33 ICSR bit assignments with the Security Extension
4-34 ID_ISAR0 bit assignments
4-35 ID_ISAR1 bit assignments
4-36 ID_ISAR2 bit assignments
4-37 ID_ISAR3 bit assignments
4-38 ID_ISAR4 bit assignments
4-39 MMFAR bit assignments
4-40 ID_MMFR0 bit assignments
4-41 ID_MMFR2 bit assignments
4-42 ID_MMFR3 bit assignments
4-43 NSACR bit assignments
4-44 SCR bit assignments without the Security Extension
4-45 SCR bit assignments with the Security Extension
4-46 SHCSR bit assignments without the Security Extension
4-47 SHCSR bit assignments with the Security Extension
4-48 System fault handler priority fields
4-49 SHPR1 register bit assignments
4-50 SHPR2 register bit assignments
4-51 SHPR3 register bit assignments
4-52 REVIDR bit assignments
4-53 VTOR bit assignments
4-54 ICB register summary
4-55 ACTLR bit assignments
4-56 ICTR bit assignments
4-57 CPPWR bit assignments
4-58 System timer registers summary
4-59 SYST_CSR bit assignments
4-60 SYST_RVR bit assignments
4-61 SYST_CVR bit assignments
4-62 SYST_CALIB_S bit assignments
4-63 SYST_CALIB_NS bit assignments
4-64 SYST_CALIB bit assignments
4-65 SYST_CALIB register bit assignments
4-66 Cache maintenance register summary
4-67 ICIALLU bit assignments
4-68 ICIMVAU bit assignments
4-69 DCIMVAC bit assignments
4-70 DCISW bit assignments
4-71 DCCMVAU bit assignments
4-72 DCCMVAC bit assignments
4-73 DCCSW bit assignments
4-74 DCCIMVAC bit assignments
4-75 DCCISW bit assignments
4-76 BPIALL bit assignments
4-77 CMSIS access cache maintenance operations
4-78 SAU registers summary
4-79 SAU_CTRL bit assignments
4-80 SAU_TYPE bit assignments
4-81 SAU_RNR bit assignments
4-82 SAU_RBAR bit assignments
4-83 SAU_RLAR bit assignments
4-84 SFSR bit assignments
4-85 SFAR bit assignments
4-86 Memory attributes summary
4-87 MPU registers summary
4-88 MPU_TYPE bit assignments
4-89 MPU_CTRL bit assignments
4-90 MPU_RNR bit assignments
4-91 MPU_RBAR bit assignments
4-92 MPU_RLAR bit assignments
4-93 MAIR_ATTR values for bits[3:2] when MAIR_ATTR[7:4] is 0000
4-94 MAIR_ATTR bit assignments when MAIR_ATTR[7:4] is not 0000
4-95 Memory region attributes for a microcontroller
4-96 Implementation defined register summary
4-97 Direct cache access registers
4-98 DCAICLR bit assignments
4-99 DCADCLR bit assignments
4-100 DCAICRR bit assignments when reading the instruction cache tag RAM
4-101 DCADCRR bit assignments when reading the data cache tag RAM
4-102 DCAICRR and DCADCRR bit assignments when reading the instruction or data cache data RAM
4-103 MSCR bit assignments
4-104 PAHBCR bit assignments
4-105 PFCR bit assignments
4-106 ITCMCR and DTCMCR bit assignments
4-107 TCM security gate registers
4-108 ITGU_CTRL and DTGU_CTRL bit assignments
4-109 ITGU_CFG and DTGU_CFG bit assignments
4-110 ITGU_LUTn and DTGU_LUTn bit assignments for implemented block mapping
4-111 Power mode control registers
4-112 CPDLPSTATE bit assignments
4-113 DPDLPSTATE bit assignments
4-114 Error bank registers
4-115 IEBR0 and IEBR1 bit assignments
4-116 DEBR0 and DEBR1 bit assignments
4-117 TEBR0 and TEBR1 bit assignments
4-118 TEBRDATA0 and TEBRDATA1 bit assignments
4-119 Processor configuration information registers
4-120 CFGINFOSEL bit assignments
4-121 Configuration parameter selection used by the CFGINFOSEL register
4-122 CFGINFOSEL bit assignments showing CFGMEMALIAS
4-123 CFGINFOSEL bit assignments showing IRQTIER when n=1
4-124 CFGINFORD bit assignments
4-125 CFGINFORD bit assignments showing CFGMEMALIAS
4-126 CFGINFORD bit assignments showing IRQTIER when n=1
4-127 EPU register summary
4-128 FPDSCR and FPSCR reset values
4-129 FPCCR bit assignments without the Security Extension
4-130 FPCCR bit assignments with the Security Extension
4-131 FPCAR bit assignments
4-132 FPSCR bit assignments
4-133 FPDSCR bit assignments
4-134 MVFR0 bit assignments
4-135 MVFR1 bit assignments
4-136 MVFR2 bit assignments
4-137 EWIC interrupt status access registers
4-138 EVENTSPR bit assignments
4-139 EVENTMASKA bit assignments
4-140 EVENTMASKn, where 0≤n≤15, bit assignments.
5-1 Cache RAM access classes
5-2 Parity checking conditions
5-3 Armv8.1‑M RAS Extension registers
5-4 ERRFR0 bit assignments
5-5 ERRSTATUS0 bit assignments
5-6 ERRADDR0 bit assignments
5-7 ERRADDR20 bit assignments
5-8 ERRMISC10 bit assignments
5-9 ERRGSR0 bit assignments
5-10 ERRDEVID bit assignments
5-11 RFSR bit assignments
6-1 PMU events
6-2 PMU register summary
6-3 PMU_EVCNTR0-7 bit assignments
6-4 PMU_CCNTR bit assignments
6-5 PMU_EVCNTR0-7 bit assignments
6-6 PMU_CNTENSET bit assignments
6-7 PMU_CNTENCLR bit assignments
6-8 PMU_INTENSET bit assignments
6-9 PMU_INTENCLR bit assignments
6-10 PMU_OVSCLR bit assignments
6-11 PMU_OVSSET bit assignments
6-12 PMU_SWINC bit assignments
6-13 PMU_TYPE bit assignments
6-14 PMU_CTRL bit assignments
6-15 PMU_AUTHSTATUS bit assignments
6-16 PMU_DEVARCH bit assignments
6-17 PMU_DEVTYPE bit assignments
6-18 PMU_PIDR0 bit assignments
6-19 PMU_PIDR1 bit assignments
6-20 PMU_PIDR2 bit assignments
6-21 PMU_PIDR3 bit assignments
6-22 PMU_PIDR4 bit assignments
6-23 PMU_CIDR0 bit assignments
6-24 PMU_CIDR1 bit assignments
6-25 PMU_CIDR2 bit assignments
6-26 PMU_CIDR3 bit assignments
A-1 EWIC register summary
A-2 EWIC_CR bit assignments
A-3 EWIC_ASCR bit assignments
A-4 EWIC_NUMID bit assignments
A-5 EWIC_MASKA bit assignments
A-6 EWIC_MASKn, where n=0-14, bit assignments
A-7 EWIC_PENDA bit assignments
A-8 EWIC_PENDn, where n=0-14, bit assignments
A-9 EWIC_PSR bit assignments
A-10 EWIC CoreSight register summary
A-11 EWIC_DEVARCH bit assignments
A-12 EWIC_AUTHSTATUS bit assignments
A-13 EWIC_PIDR4 bit assignments
A-14 EWIC_PIDR5 bit assignments
A-15 EWIC_PIDR6 bit assignments
A-16 EWIC_PIDR7 bit assignments
A-17 EWIC_PIDR0 bit assignments
A-18 EWIC_PIDR1 bit assignments
A-19 EWIC_PIDR2 bit assignments
A-20 CTI_PIDR3 bit assignments
A-21 EWIC_CIDR0 bit assignments
A-22 EWIC_CIDR1 bit assignments
A-23 EWIC_CIDR2 bit assignments
A-24 EWIC_CIDR3 bit assignments
B-1 Issue 0001-01

Release Information

Document History
Issue Date Confidentiality Change
0001-01 31 March 2020 Non-Confidential First early access release for r0p0

Non-Confidential Proprietary Notice

This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of Arm. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated.

Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents.

THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, Arm makes no representation with respect to, and has undertaken no analysis to identify or understand the scope and content of, third party patents, copyrights, trade secrets, or other rights.

This document may include technical inaccuracies or typographical errors.


This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof is not exported, directly or indirectly, in violation of such export laws. Use of the word “partner” in reference to Arm’s customers is not intended to create or refer to any partnership relationship with any other company. Arm may make changes to this document at any time and without notice.

If any of the provisions contained in these terms conflict with any of the provisions of any click through or signed written agreement covering this document with Arm, then the click through or signed written agreement prevails over and supersedes the conflicting provisions of these terms. This document may be translated into other languages for convenience, and you agree that if there is any conflict between the English version of this document and any translation, the terms of the English version of the Agreement shall prevail.

The Arm corporate logo and words marked with ® or ™ are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. Other brands and names mentioned in this document may be the trademarks of their respective owners. Please follow Arm’s trademark usage guidelines at

Copyright © 2020 Arm Limited (or its affiliates). All rights reserved.

Arm Limited. Company 02557590 registered in England.

110 Fulbourn Road, Cambridge, England CB1 9NJ.


Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to.

Unrestricted Access is an Arm internal classification.

Product Status

The information in this document is Final, that is for a developed product.

Web Address

Non-ConfidentialPDF file icon PDF version101273_0001_01_en
Copyright © 2020 Arm Limited or its affiliates. All rights reserved.