Arm® SSE‑123 Example Subsystem Technical Reference Manual

Revision r0p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback
Feedback on this product
Feedback on content
1 Introduction
1.1 About the SSE-123 Example Subsystem
1.2 About IoT System on Chip implementations
1.2.1 IoT hardware and software
1.3 Compliance
1.3.1 Arm architecture
1.3.2 Security architecture
1.3.3 Interrupt controller architecture
1.3.4 Advanced Microcontroller Bus Architecture (AMBA®)
1.3.5 Debug architecture
1.3.6 Power control architecture
1.4 Features of SSE-123
1.5 Configurable options
1.5.1 Subsystem configuration options
1.5.2 Processor configuration options
1.6 Product documentation
1.6.1 Documentation
1.7 Product revisions
2 Functional description
2.1 Clocks
2.1.1 Clock control
2.1.2 External wakeup
2.1.3 Clock domain expansion
2.1.4 FCLK dynamic clock switching
2.2 Resets
2.2.1 Internally generated resets
2.2.2 Reset requests
2.2.3 Reset control
2.3 Power management
2.3.1 Voltage domain
2.3.2 Power domains
2.3.3 Subsystem power states
2.3.4 Entering low‑power states
2.3.5 Wakeup from low‑power states
2.3.6 Power domain expansion
2.3.7 Wakeup Interrupt Controller (WIC) and WIC-bridge
2.4 Central processor
2.4.1 Implementation Defined Attribution Unit (IDAU)
2.4.2 Processor interface expansion
2.5 Interconnect
2.5.1 Interconnect expansion interfaces
2.5.2 Exclusive access support
2.6 Debug
2.6.1 Debug authentication
2.6.2 Debug Access Port (DAP)
2.6.3 Cross triggers
2.6.4 Trace
2.6.5 Debug expansion
2.7 Security control
2.7.1 Peripheral protection controller
2.7.2 Memory protection controller
2.7.3 Security expansion
2.8 Peripherals
2.8.1 Subsystem Timers
2.8.2 Subsystem watchdogs
2.9 Subsystem SRAM
3 Programmers model
3.1 About the programmers model
3.2 Subsystem memory map
3.3 Subsystem register descriptions
3.3.1 Subsystem information registers block
3.3.2 Subsystem control registers block
3.3.3 Secure privilege control registers block
3.3.4 Non-secure privilege control registers block
3.3.5 Subsystem timers
3.3.6 Subsystem watchdogs
3.3.7 Power Policy Unit (PPU)
3.3.8 SRAM memory protection control
3.3.9 Cortex-M23 processor Private Peripheral Bus (PPB)
3.4 Subsystem interrupt map
A Signal descriptions
A.1 Clock signals
A.2 Reset signals
A.3 Clock control interface signals
A.4 HCLK clock Q‑Channel signals
A.5 DCLK clock Q-Channel signals
A.6 Entry delay signals
A.7 Clock enable signals
A.8 Reset control interface signals
A.9 Power control interfaces
A.9.1 PD_SYS power Q‑Channel signals
A.9.2 Debug power interface signals
A.9.3 PPU power mode status signal
A.10 Expansion interfaces
A.10.1 AHB5 expansion master interface 0
A.10.2 AHB5 expansion master interface 1
A.10.3 AHB5 expansion slave interface
A.10.4 Single cycle I/O interface signals
A.11 Interrupt signals
A.12 Timestamp signals
A.13 Event signals
A.14 Debug interfaces
A.14.1 Debug authentication signals
A.14.2 Debug slave interface signals
A.14.3 ATB ETM slave interface signals
A.14.4 ETM control signals
A.14.5 Cross Trigger Interface signals
A.14.6 APB debug expansion master interface signals
A.15 Security control expansion signals
A.16 Static configuration signals
A.17 System control signals
A.18 System status signals
A.19 DFT interface signals
B System time components
B.1 About system time components
B.2 System Counter
B.2.1 System Counter overview
B.2.2 Counter operation
B.2.3 Programmers model
B.3 System Timer
B.3.1 System Timer overview
B.3.2 System Timer operation
B.3.3 Programmers model
B.4 System Watchdog
B.4.1 System Watchdog overview
B.4.2 Watchdog operation
B.4.3 Programmers model
C Revisions
C.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000 22 March 2019 Non-Confidential First release for r0p0

Non-Confidential Proprietary Notice

This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of Arm. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated.

Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents.

THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, Arm makes no representation with respect to, and has undertaken no analysis to identify or understand the scope and content of, third party patents, copyrights, trade secrets, or other rights.

This document may include technical inaccuracies or typographical errors.

TO THE EXTENT NOT PROHIBITED BY LAW, IN NO EVENT WILL ARM BE LIABLE FOR ANY DAMAGES, INCLUDING WITHOUT LIMITATION ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING OUT OF ANY USE OF THIS DOCUMENT, EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof is not exported, directly or indirectly, in violation of such export laws. Use of the word “partner” in reference to Arm’s customers is not intended to create or refer to any partnership relationship with any other company. Arm may make changes to this document at any time and without notice.

If any of the provisions contained in these terms conflict with any of the provisions of any click through or signed written agreement covering this document with Arm, then the click through or signed written agreement prevails over and supersedes the conflicting provisions of these terms. This document may be translated into other languages for convenience, and you agree that if there is any conflict between the English version of this document and any translation, the terms of the English version of the Agreement shall prevail.

The Arm corporate logo and words marked with ® or ™ are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. Other brands and names mentioned in this document may be the trademarks of their respective owners. Please follow Arm’s trademark usage guidelines at http://www.arm.com/company/policies/trademarks.

Copyright © 2019 Arm Limited (or its affiliates). All rights reserved.

Arm Limited. Company 02557590 registered in England.

110 Fulbourn Road, Cambridge, England CB1 9NJ.

LES-PRE-20349

Additional Notices

Some material in this document is based on IEEE 754-2008 IEEE Standard for Binary Floating-Point Arithmetic. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to.

Unrestricted Access is an Arm internal classification.

Product Status

The information in this document is Final, that is for a developed product.

Web Address

Non-ConfidentialPDF file icon PDF version101370_0000_0000_en
Copyright © 2019 Arm Limited or its affiliates. All rights reserved.