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The AHB5 to AXI5 bridge provides two Q-Channel interfaces. One Q-Channel is intended for clock control and the other Q-Channel for power control.
Both Q-Channels implement the low-power interfaces that the AMBA® Low Power Interface Specification, Arm® Q-Channel and P-Channel Interfaces describes.
The Q-Channels deny quiescent requests when there is ongoing activity or outstanding transactions. Incoming transfers are halted when the bridge is in quiescent state.
If the bridge receives a wakeup request on the power channel, then it asserts clk_qactive because the bridge requires the clock during the wakeup process.
A synchronizer is always present on the pwr_qreqn input of the power Q-Channel. The presence of a synchronizer on the clk_qreqn input of the clock Q-Channel is configurable, by using the QCLK_SYNC_EN parameter.