A.2 AHB5 to AXI5 bridge signals

The bridge has signals for an AHB5 slave interface and an AXI5 master interface. The bridge also has Q-Channel, interrupt, and sideband signals.

The following table lists the clock and reset signals.

Table A-7 Clock and reset signals

Signal Direction Description
clk Input Clock
resetn Input Active-LOW reset. Reset can go LOW asynchronously but must go HIGH synchronously.

The following table shows the AHB5 slave interface signals. For more information about the AMBA® AHB5 signals, see the Arm® AMBA® 5 AHB Protocol Specification.

Table A-8 AHB5 slave interface signals

Signal Direction Description
hsel Input This signal selects the AHB5 slave interface.
hnonsec Input Security level, asserted to indicate a Non-secure transfer.
haddr[ADDR_WIDTH−1:0] Input Transfer address.
htrans[1:0] Input Transfer type.
hsize[2:0] Input Transfer size.
hwrite Input Write transfer.
hready Input Transfer completion indicator.
hprot[6:0] Input Protection control.
hburst[2:0] Input Transfer burst length.
hmastlock Input Locked sequence indicator.
hwdata[DATA_WIDTH−1:0] Input Write data.
hexcl Input Exclusive Transfer indicator.
hmaster[ID_WIDTH−1:0] Input Master identifier.
hrdata[DATA_WIDTH−1:0] Output Read data.
hreadyout Output Slave ready.
hresp Output Slave response.
hexokay Output Exclusive okay.
hauser[USER_AX_WIDTH−1:0] Input Address channel User signals.
hruser[USER_R_WIDTH−1:0] Output Read data channel User signals.
hwuser[USER_W_WIDTH−1:0] Input Write data channel User signals.

The following table shows the sideband signals for the AHB5 slave interface. These signals are not present in the AHB5 protocol.

Table A-9 AHB5 slave interface sideband signals

Signal Direction Description
hqos[3:0] Input QoS signal
hregion[3:0] Input Region identifier signal
hnsaid[3:0] Input Non-secure Access Identifier (NSAID) signal

The following table shows the interrupt signal, and its enable signal, for the AHB5 to AXI5 bridge.

Table A-10 Interrupt signals for the AHB5 to AXI5 bridge

Signal Direction Description
buf_write_error_irq Output

Active-HIGH pulse interrupt.

If the bridge receives an ERROR response for a buffered write, then this signal goes HIGH for 1 clk cycle. See 3.9 Early write response and RAW hazard.

If the bridge receives an ERROR response for an early terminated write, then this signal goes HIGH for 1 clk cycle. An early terminated write can also occur for a Modifiable undefined length burst that the bridge transfers as one or more 4-beat bursts. See Undefined length bursts.

irq_en Input Interrupt enable:
  • HIGH = Enables the buf_write_error_irq interrupt.
  • LOW = Disables the buf_write_error_irq interrupt.

The following table shows the AXI5 master interface signals. For more information about the AMBA AXI5 signals, see the Arm® AMBA® AXI and ACE Protocol Specification.

Table A-11 AXI5 master interface signals

Signal Direction Description
AW channel signals:
awvalid Output Write address valid signal.
awaddr[31:0] Output Write address signal.
awdomain[1:0] Output Indicates the shareability domain of a write transaction.
awburst[1:0] Output Write burst type signal.
awid[ID_WIDTH−1:0] Output Write request ID signal.
awlen[7:0] Output Write burst length signal.
awsize[2:0] Output Write burst size signal.
awlock Output Write lock type signal.
awprot[2:0] Output Write protection type signal.
awready Input Write address ready signal.
awcache[3:0] Output Indicates how transactions are required to progress through a system.
awregion[3:0] Output Permits a single physical interface on a slave to be used for multiple logical interfaces.
awnsaid[3:0] Output Provides extra access controls for writes to Non-secure memory locations.
awqos[3:0] Output QoS identifier.
awuser[USER_AX_WIDTH−1:0] Output Write address channel User signals.
AR channel signals:
arvalid Output Read address valid signal.
araddr[31:0] Output Read address signal.
ardomain[1:0] Output Indicates the shareability domain of a read transaction.
arburst[1:0] Output Read burst type signal.
arid[ID_WIDTH−1:0] Output Read request ID signal.
arlen[7:0] Output Read address burst length signal.
arsize[2:0] Output Read burst size signal.
arlock Output Read lock type signal.
arprot[2:0] Output Read protection type signal.
arready Input Read address ready signal.
arcache[3:0] Output Indicates how transactions are required to progress through a system.
arregion[3:0] Output Permits a single physical interface on a slave to be used for multiple logical interfaces.
arnsaid[3:0] Output Provides extra access controls for reads from Non-secure memory locations.
arqos[3:0] Output QoS identifier.
aruser[USER_AX_WIDTH−1:0] Output Read address channel User signals.
W channel signals:
wvalid Output Write data valid signal.
wlast Output Indicates last transfer in a write burst.
wstrb[(DATA_WIDTH/8)−1:0] Output Write byte lane strobes.
wdata[DATA_WIDTH−1:0] Output Write data signal.
wuser[USER_W_WIDTH−1:0] Output Write channel User signals.
wready Input Write data ready signal.
R channel signals:
rvalid Input Read data valid signal.
rid[ID_WIDTH−1:0] Input Read data ID.
rlast Input Indicates last transfer in read data.
rdata[DATA_WIDTH−1:0] Input Read data.
ruser[USER_R_WIDTH−1:0] Input Read channel User signals.
rresp[1:0] Input Read data response.
rready Output Read data ready signal.
B channel signals:
bvalid Input Read data valid signal.
bid[ID_WIDTH−1:0] Input Read data ID signal.
bresp[1:0] Input Write response signal.
bready Output Write response ready signal.

The following table lists a low-power signal for the AXI5 master interface.

Table A-12 AXI5 master interface low-power signal

Signal Direction Description
awakeup Output Indicates that the bridge is processing an AXI transaction. awakeup is HIGH when any of the following occur:
  • htrans is not in the IDLE state.
  • The write buffer is not empty.
  • The internal Finite State Machines (FSMs) are not idle.

The following table lists the Q-Channel signals.

Table A-13 Q-Channel signals for the AHB5 to AXI5 bridge

Signal Direction Description
Clock control Q-Channel signals:
clk_qreqn Input This signal indicates when the controller issues a quiescence entry or exit request to the bridge.
clk_qacceptn Output This signal indicates when the bridge accepts the quiescence request.
clk_qdeny Output This signal indicates when the bridge denies the quiescence request.
clk_qactive Output This signal indicates when the bridge is active or it is requesting to exit from quiescence.
Power control Q-Channel signals:
pwr_qreqn Input

This signal indicates when the controller issues a quiescence entry or exit request to the bridge.

The input contains a 2-stage synchronizer, so the signal can transition asynchronously.

pwr_qacceptn Output This signal indicates when the bridge accepts the quiescence request.
pwr_qdeny Output This signal indicates when the bridge denies the quiescence request.
pwr_qactive Output This signal indicates when the bridge is active or it is requesting to exit from quiescence.
Non-Confidential - BetaPDF file icon PDF version101375_0000_00_en
Copyright © 2018 Arm Limited or its affiliates. All rights reserved.