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|Home > Functional Description, AHB5 to AXI5 bridge > Early write response and RAW hazard|
An early write response is when the AHB5 to AXI5 bridge provides the AHB5 write response before it receives the AXI write response.
The AHB5 to AXI5 bridge provides an early write response for AHB write transfers that are Bufferable (hprot is HIGH) and Non-shareable (hprot is LOW).
If the bridge responds OKAY to an AHB buffered write and then later the AXI response is ERROR, the bridge pulses the buf_write_error_irq interrupt signal for 1 clk cycle, when irq_en is HIGH. Setting the interrupt enable, irq_en, signal LOW, disables the generation of buf_write_error_irq interrupts.
To avoid Read After Write (RAW) hazards, the bridge stores the last 4 AXI write addresses that are waiting for write responses. The bridge stalls any read with an address that matches the same 4K region, until the write response arrives. If there are 4 writes waiting for an AXI write response, the bridge does not provide an early write response for a 5th write until one of the previous 4 writes completes.