1.1 About the XHB-500 bridges

The XHB-500 product provides an AMBA® AXI5 to AHB5 bridge and an AHB5 to AXI5 bridge.

The AXI5 to AHB5 bridge translates AXI5 transactions into the corresponding AHB transfers. The bridge has an AXI5 slave interface and an AHB5 master interface.

The AHB5 to AXI5 bridge translates AHB5 transfers into the corresponding AXI transactions. The bridge has an AHB5 slave interface and an AXI5 master interface.

AXI5 to AHB5 bridge overview

The AXI5 to AHB5 is a low-latency bridge that performs no transaction buffering.

The following figure shows the interfaces of the AXI5 to AHB5 bridge.

Figure 1-1 AXI5 to AHB5 interfaces
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The main features are:

  • Single power domain.
  • Single clock domain.
  • Configurable data width.
  • AXI5 slave interface features:
    • AXI5 protocol support.
    • AXI4 protocol support.
    • Fixed address width.
    • Registered or unregistered interface.
    • Single Exclusive accesses. Exclusive bursts are not supported.
    • Unaligned accesses.
    • Conversion of sparse write transactions, when the HWSTRB_ENABLE configuration parameter is set to OFF.
    • Supports all burst types.
  • AHB5 master interface features:
    • AHB5 support.
    • AHB-Lite support, which requires several signals to be tied off.
    • Fixed address width.
    • Registered or unregistered interface.
    • Exclusive accesses. For AHB-Lite, extra glue logic is required.
    • No support for locked transfers.
    • Write strobe support using the hwstrb signal, when the HWSTRB_ENABLE configuration parameter is set to ON. The hwstrb signal is not present in the Arm® AMBA® 5 AHB Protocol Specification.
  • Q-Channel interface for clock control.
  • Q-Channel interface for power control.

The bridge does not support endian conversion.

AHB5 to AXI5 bridge overview

The AHB5 to AXI5 is a low-latency bridge.

The following figure shows the interfaces of the AHB5 to AXI5 bridge.

Figure 1-2 AHB5 to AXI5 interfaces
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The main features are:

  • Single power domain.
  • Single clock domain.
  • Configurable data width.
  • AHB5 slave interface features:
    • AHB5 protocol support.
    • Fixed address width.
    • Registered or unregistered interface.
    • Support for early write response.
    • Supports all burst types.
  • AXI5 master interface features:
    • AXI5 support.
    • Fixed address width.
    • Registered or unregistered interface.
    • RAW hazard checking for early write response.
  • Buffered write error interrupt.
  • Q-Channel interface for clock control.
  • Q-Channel interface for power control.

The bridge does not support endian conversion.

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