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Although the AHB protocol does not support write strobes, the AXI5 to AHB5 bridge provides two methods to handle an AXI sparse write transaction. During implementation of the bridge, the setting of the HWSTRB_ENABLE configuration option controls which method the bridge implements.
== OFF, the bridge uses the awsparse and wstrb inputs to control how it issues AHB write transfers that contain sparse data. awsparse is a sideband signal that an AXI master can assert for any write transaction, including unaligned writes, that might contain sparse beats. When awsparse is HIGH, the bridge checks the wstrb strobe lanes for every AXI beat, and splits the beat into several AHB transfers if byte lanes are omitted. To issue the minimum number of transfers, the bridge uses the largest possible aligned transfer size. The mapping process does not insert any delay cycles to the transaction. The bridge propagates all bursts as INCR transfers, to optimize for non-sparse burst translations that awsparse might pessimistically indicate.
The bridge gives priority to reads over writes. Therefore, a read burst always executes to completion, but the bridge can stall a sparse write transaction when it receives a read burst. Sparse write transactions continue after the read burst completes. See 2.11 Read and write transaction scheduling.
== ON, the AHB master interface includes a write strobe sideband signal, hwstrb, and the AXI slave interface does not have an awsparse input. For a write transaction, the AXI5 to AHB5 bridge copies the wstrb value to hwstrb. Any AHB slave that supports write strobes, can use hwstrb to select the byte lanes that hold valid data.
The bridge aligns any unaligned AXI addresses and uses the strobes to convey the unalignment information, and it translates the bursts as if they were not sparse. See 2.2 Burst conversions for more information.