2.7 Address alignment

The AXI and AHB protocols handle transaction addresses differently, so the AXI5 to AHB5 bridge must perform address alignment. The AHB protocol does not support unaligned transfers.

In AXI, the master issues only the starting address for the whole transaction and it is the responsibility of the slave to increment the address for the transaction beats. The AXI address can be unaligned to the boundary that axsize[2:0] determines, although it is only the first beat that is unaligned, the remaining beats are aligned. In AHB, the master calculates and issues all beat addresses in a burst and each beat is aligned.

Therefore, the AXI5 to AHB5 calculates aligned AHB addresses for all beats from the incoming single AXI address. The bridge can either align the address or split the AXI transaction into several aligned AHB beats. The bridge also calculates wrap addresses.

When the bridge receives:

An unaligned write transaction
The bridge treats the transaction as a sparse transaction, with the restriction that the address (awaddr[31:0]) and wstrb signals must be consistent. Since the first beat is always sparse, the AXI master must drive awsparse HIGH if the bridge is configured with HWSTRB_ENABLE == OFF.
Modifiable unaligned read transaction
The bridge aligns the address, so the first beat of the burst contains more data than the AXI master expects. The AXI master can ignore the extra data.
Non-modifiable unaligned read transaction

A Non-modifiable read transaction is not permitted to perform a speculative read of Device memory, so:

  • If the AXI burst type is INCR or WRAP, then the bridge splits the first AXI transfer into several aligned AHB beats, transferring the largest possible aligned beats. The bridge transfers the remainder of the transaction as an undefined length AHB INCR burst.
  • For AXI FIXED bursts, the bridge splits the transaction so that all the AHB beats are aligned.
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