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|Home > Functional Description, AHB5 to AXI5 bridge > Response generation|
When an AHB slave is idle, it always asserts hreadyout and sets hresp LOW, which indicates no errors. Therefore, the bridge always accepts a transfer if there is no pending data phase transaction. In the data phase:
For reads, the bridge transfers any AXI error responses that occur.
For writes, the bridge returns an OKAY response for each AHB beat except for the final beat, when it returns the response from the AXI B channel.
AHB allows early termination of bursts. If a burst is broken on AHB, the bridge still completes the AXI transaction, but it discards read data and masks off write data, and it discards any AXI error responses during the transaction.
If the bridge receives a write error response, then it pulses the buf_write_error_irq interrupt signal for 1 clk cycle. The bridge generates an interrupt because the error might relate to write beats that occur before the AHB master signals the early termination of a burst.