3.2 Burst translation

For most of the AHB burst types, the AHB5 to AXI5 bridge can perform a simple translation to create the AXI burst. However, the bridge requires extra logic to cope with undefined length bursts and early burst termination.

Undefined length bursts

The bridge converts Modifiable undefined length incremental bursts to transactions of burst length 1 or burst length 4. The INCR_BURST_CONV Verilog parameter controls the length of the AXI burst.

If INCR_BURST_CONV is set to a burst length of four and the AHB master prematurely stops the burst, then the bridge still completes the four bursts, except:

  • For reads, the bridge discards the extra read data.
  • For writes, the bridge sets wstrb LOW.

Early burst termination

If an AHB read burst is terminated early, the bridge completes the remainder of the burst but it discards the extra read data.

If an AHB write burst is terminated early, the bridge sets the byte strobes to zero and it discards the extra write response. If the discarded write response contains an error, the bridge pulses the buf_write_error_irq interrupt signal for 1 clk cycle.

Note:

  • An AHB burst might terminate prematurely because:

    • The AHB master receives an ERROR response so it terminates the burst early.
    • The interconnect terminates the burst early.
    • The bridge promotes an undefined length burst to INCR4 and the ending of the AHB burst does not coincide with the AXI burst length.
  • Early burst termination can also cause issues when the bridge is accessing Device memory. Therefore, to prevent the bridge from performing speculative reads of Device memory, the bridge converts Non-modifiable transfers to single AXI transactions.
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