A.1 AXI5 to AHB5 bridge signals

The bridge has signals for an AXI5 slave interface and an AHB5 master interface. The bridge also has Q-Channel and sideband signals.

The following table lists the clock and reset signals.

Table A-1 Clock and reset signals

Signal Direction Description
clk Input Clock
resetn Input Active-LOW reset. Reset can go LOW asynchronously but must go HIGH synchronously.

The following table lists the AXI5 slave interface signals.

Table A-2 AXI5 slave interface signals

Signal Direction Description
AW channel signals:
awvalid Input Write address valid signal.
awaddr[31:0] Input Write address signal.
awdomain[1:0] Input Used for creating an AHB shareable protection control bit for read transactions.
awburst[1:0] Input Write burst type signal.
awid[ID_WIDTH−1:0] Input Write request ID signal.
awlen[7:0] Input Write burst length signal.
awsize[2:0] Input Write burst size signal.
awlock Input Write lock type signal.
awprot[2:0] Input Write protection type signal.
awready Output Write address ready signal.
awcache[3:0] Input Indicates how transactions are required to progress through a system.
awregion[3:0] Input Permits a single physical interface on a slave to be used for multiple logical interfaces.
awnsaid[3:0] Input Provides extra access controls for writes to Non-secure memory locations.
awloop[LB_WIDTH−1:0] Input Value to return on the B channel loopback signal, bloop.
awqos[3:0] Input QoS identifier.
awuser[USER_AX_WIDTH−1:0] Input User-defined signal.
AR channel signals:
arvalid Input Read address valid signal.
araddr[31:0] Input Read address signal.
ardomain[1:0] Input Used for creating an AHB shareable protection control bit for read transactions.
arburst[1:0] Input Read burst type signal.
arid[ID_WIDTH−1:0] Input Read request ID signal.
arlen[7:0] Input Read address burst length signal.
arsize[2:0] Input Read burst size signal.
arlock Input Read lock type signal.
arprot[2:0] Input Read protection type signal.
arready Output Read address ready signal.
arcache[3:0] Input Indicates how transactions are required to progress through a system.
arregion[3:0] Input Permits a single physical interface on a slave to be used for multiple logical interfaces.
arnsaid[3:0] Input Provides extra access controls for reads to Non-secure memory locations.
arloop[LB_WIDTH−1:0] Input Value to return on the R channel loopback signal, rloop.
arqos[3:0] Input QoS identifier.
aruser[USER_AX_WIDTH−1:0] Input User-defined signal.
W channel signals:
wvalid Input Write data valid signal.
wlast Input Indicates last transfer in a write burst.
wstrb[(DATA_WIDTH/8)−1:0] Input Write byte lane strobes.
wdata[DATA_WIDTH−1:0] Input Write data signal.
wuser[USER_W_WIDTH−1:0] Input User-defined signal.
wready Output Write data ready signal.
R channel signals:
rvalid Output Read data valid signal.
rid[ID_WIDTH−1:0] Output Read data ID.
rlast Output Indicates last transfer in read data.
rdata[DATA_WIDTH−1:0] Output Read data.
ruser[USER_R_WIDTH−1:0] Output User-defined signal.
rresp[1:0] Output Read data response.
rready Input Read data ready signal.
rloop[LB_WIDTH−1:0] Output Return path for the AR channel loopback signal, arloop.
B channel signals:
bvalid Output Read data valid signal.
bid[ID_WIDTH−1:0] Output Read data ID signal.
bresp[1:0] Output Write response signal.
bready Input Write response ready signal.
bloop[LB_WIDTH−1:0] Output Return path for the AW channel loopback signal, awloop.

The following table lists the low-power and sideband signals on the AXI5 slave interface.

Table A-3 AXI5 slave interface low-power signal and sideband signal

Signal Direction Description
Low-power signals:
awakeup Input Indicates that the AXI master is initiating activity on this interface.
Sideband signals:
awsparse Input Set this signal HIGH, if an AXI burst might use sparse writes strobes. This signal is not present in the AXI5 protocol.

The following table lists the AHB5 master interface signals.

Table A-4 AHB5 master interface signals

Signal Direction Description
hnonsec Output Security level, asserted to indicate a Non-secure transfer.
haddr[ADDR_WIDTH−1:0] Output Transfer address.
htrans[1:0] Output Transfer type.
hsize[2:0] Output Transfer size.
hwrite Output Write transfer.
hready Input Transfer completion indicator.
hprot[6:0] Output Protection control.
hburst[2:0] Output Transfer burst length.
hmastlock Output Locked sequence indicator.
hwdata[DATA_WIDTH−1:0] Output Write data.
hexcl Output Exclusive Transfer indicator.
hmaster[ID_WIDTH−1:0] Output Master identifier.
hrdata[DATA_WIDTH−1:0] Input Read data.
hresp Input Slave response.
hexokay Input Exclusive okay.
hauser[USER_AX_WIDTH−1:0] Output Address channel User signals.
hruser[USER_R_WIDTH−1:0] Input Read data channel User signals.
hwuser[USER_W_WIDTH−1:0] Output Write data channel User signals.

The following table lists the sideband signals on the AHB5 master interface.

Table A-5 AHB5 master interface sideband signals

Signal Direction Description
hqos[3:0] Output QoS signal
hregion[3:0] Output Region identifier signal
hnsaid[3:0] Output Non-secure Access Identifier (NSAID) signal
hwstrb[(DATA_WIDTH/8)−1:0] Output Replicates the wstrb content, when the HWSTRB_ENABLE parameter is set to ON.

The following table lists the Q-Channel signals.

Table A-6 Q-Channel signals for the AXI5 to AHB5 bridge

Signal Direction Description
Clock control Q-Channel signals:
clk_qreqn Input This signal indicates when the controller issues a quiescence entry or exit request to the bridge. The QCLK_SYNC_EN parameter controls whether this input includes a 2-stage synchronizer.
clk_qacceptn Output This signal indicates when the bridge accepts the quiescence request.
clk_qdeny Output This signal indicates when the bridge denies the quiescence request.
clk_qactive Output This signal indicates when the bridge is active or it is requesting to exit from quiescence.
Power control Q-Channel signals:
pwr_qreqn Input

This signal indicates when the controller issues a quiescence entry or exit request to the bridge.

The input contains a 2-stage synchronizer, so the signal can transition asynchronously.

pwr_qacceptn Output This signal indicates when the bridge accepts the quiescence request.
pwr_qdeny Output This signal indicates when the bridge denies the quiescence request.
pwr_qactive Output This signal indicates when the bridge is active or it is requesting to exit from quiescence.
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