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The AXI5 to AHB5 bridge supports four AXI User signals and three AHB User signals. The signal width of the address User signals, the read User signals, and the write User signals can be configured to different values.
The following table shows how these signals are mapped between the interfaces.
Table 2-7 User sideband signals mapping
|AXI5 slave interface||AHB5 master interface||Comment|
Read transfers. The same hauser value is output on each beat that is associated with an AXI5 transaction.
|awuser||Write transfers. The same hauser value is output on each beat that is associated with an AXI5 transaction.|
Only valid on write transfers.
For non-sparse writes, the bridge separately translates each beat, and the respective hwuser equals wuser for all beats.
If a transfer is sparse, one AXI transfer might translate to multiple AHB beats, so the wuser value repeats on hwuser.
Only valid on read transfers. The value might differ on each beat.
The last hruser is propagated when multiple AHB transfers are accumulated for the first beat of an unaligned Non-modifiable read.