2.10 Register slices

The bridge offers flexibility in the timing of its interfaces with configurable register slices on each slave and master interface.

AXI register slices

Each AXI channel has a register slice. During configuration, you can configure a register slice to operate in one of the following modes:

BYPASSThe register slice is bypassed and inserts zero latency.
FORWARDThe forward register slice provides timing isolation in only the forward direction, that is, the valid signal and the payload of that AXI channel. The register slice inserts 1 clk cycle of latency.
REVERSEThe reverse register slice provides timing isolation in only the reverse direction, that is, the ready signal and the payload of that AXI channel. The register slice inserts a minimum of zero clk cycle of latency and a maximum of 1 clk cycle of latency.
FULLThe full register slice provides timing isolation in the forward and reverse directions. The register slice inserts a minimum of 1 clk cycle of latency and a maximum of:
  • 2 clk cycles of latency on the AR, AW, and W channels.
  • 1 clk cycle of latency on the R and B channels.

AHB register slices

During configuration, you can add the following register slices:

CNTRLThe control register slice provides timing isolation for the address phase and hwdata paths.
RDATA

This register slice provides timing isolation for hrdata and hready paths.

The bridge core logic detects an hready falling edge one clk cycle later than it occurs, so temporary storage is included on the AHB output signals to hold the values during the transient cycle.

Latency calculations for read transfers

If no register slices are enabled, then the bridge can potentially perform read transfers with no added latency. However, due to the pipeline behavior of AHB, there is always 1 cycle of latency.

When there are no added wait states, the minimum and maximum read latencies are:

read_latency(min)

= 1 + lat(AXI_AR) + AHB_REG_CNTRL + AHB_REG_RDATA(addr) + AHB_REG_RDATA(resp) + lat(AXI_R)

= 1 + 0 + 0 + 0 + 0 + 0

= 1 clk cycle of latency.

read_latency(max)

= 1 + lat(AXI_AR) + AHB_REG_CNTRL + AHB_REG_RDATA(addr) + AHB_REG_RDATA(resp) + lat(AXI_R)

= 1 + 2 + 1 + 1 + 2 + 1

= 8 clk cycles of latency. This latency occurs for a fully registered bridge, that is, the AXI register slices set to FULL and the AHB read data and control register slices enabled.

Wait states occur when the slave is not ready or the read data is delayed.

Latency calculations for write transfers

The AXI protocol requires that the B channel write response must always follow the last W channel write transfer, so there is always 1 clk cycle of latency.

The AW channel latency is excluded, because it does not delay the write data channel.

When there are no added wait states, the minimum and maximum write latencies are:

write_latency(min)

= 1 + lat(max(AXI_AW, AXI_W)) + AHB_REG_CNTRL + AHB_REG_WDATA(addr) + AHB_REG_WDATA(resp) + lat(AXI_B)

= 1 + 0 + 0 + 0 + 0 + 0

= 1 clk cycle of latency.

write_latency(max)

= 1 + lat(max(AXI_AW, AXI_W)) + AHB_REG_CNTRL + AHB_REG_WDATA(addr) + AHB_REG_WDATA(resp) + lat(AXI_B)

= 1 + 2 + 1 + 1 + 2 + 1

= 8 clk cycles of latency. This latency occurs for a fully registered bridge, that is, the AXI register slices set to FULL and the AHB write data and control register slices enabled.

AXI transaction acceptance capabilities

The acceptance capabilities depend on whether the AR or AW channels are registered. The combined acceptance also depends on the setting of the HWSTRB_ENABLE parameter.

The following table lists the AXI acceptance capabilities.

Table 2-8 AXI acceptance capabilities

Capability Value Notes
Read acceptance. 1 + AR acceptance

The value of AR acceptance is:

0, when AR channel register slice is in BYPASS.

1, when AR channel register slice is in FORWARD or REVERSE.

2, when AR channel register slice is in FULL.

Write acceptance. 1 + AW acceptance

The value of AW acceptance is:

0, when AW channel register slice is in BYPASS.

1, when AW channel register slice is in FORWARD or REVERSE.

2, when AW channel register slice is in FULL.

Combined acceptance. 1 + AR acceptance + AW acceptance When HWSTRB_ENABLE == ON.
2 + AR acceptance + AW acceptance When HWSTRB_ENABLE == OFF.
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