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|Home > Functional Description, AHB5 to AXI5 bridge > Register slices|
The bridge offers flexibility in the timing of its interfaces with configurable register slices on each slave and master interface.
During configuration, you can add the following register slices:
|CNTRL||The control register slice provides timing isolation for the address phase paths.|
|RDATA||This register slice provides timing isolation for the hrdata path, the response, and the write response.|
|WDATA||This register slice provides timing isolation for the hwdata path.|
A register slice includes the corresponding User signal, that is, hauser, hruser, or hwuser.
Each AXI channel can include a register slice. During configuration, you can configure a register slice to operate in one of the following modes:
|BYPASS||A register slice is not instantiated on the AXI channel.|
|FORWARD||The forward register slice inserts 1 clk cycle of latency and provides timing isolation in only the forward direction, that is, the valid signal and the payload of that AXI channel.|
|REVERSE||The reverse register slice inserts 0-1 clk cycle of latency and provides timing isolation in only the reverse direction, that is, the ready signal and the payload of that AXI channel.|
|FULL||The full register slice inserts 1-2 clk cycles of latency and provides timing isolation in the forward and reverse directions.|
If no register slices are enabled, then the bridge can potentially perform read transfers with no added latency. If all registering is enabled the read latency is 4-6 clk cycles, depending on whether the connected slave has arready and rready HIGH.
When there are no added wait states, the read latency is:
Wait states occur when the slave is not ready or the read data is delayed.
A write transfer can only have zero latency if the bridge can provide an early write response. Otherwise, the AXI protocol requires that the B channel write response must always follow the last W channel write transfer, which results in one extra clk cycle.
The AW channel latency is excluded, because it does not delay the write data channel.
If the bridge can provide an early write response, then for a single beat write the latency is:
If the bridge cannot provide an early write response, the latency is:
If all registering is enabled on both AHB and AXI, then the minimum write latency is 6 clk cycles (5 wait states are inserted). The maximum write latency is 8 clk cycles.