3.10 Register slices

The bridge offers flexibility in the timing of its interfaces with configurable register slices on each slave and master interface.

AHB register slices

During configuration, you can add the following register slices:

CNTRLThe control register slice provides timing isolation for the address phase paths.
RDATAThis register slice provides timing isolation for the hrdata path, the response, and the write response.
WDATAThis register slice provides timing isolation for the hwdata path.

A register slice includes the corresponding User signal, that is, hauser, hruser, or hwuser.

AXI register slices

Each AXI channel can include a register slice. During configuration, you can configure a register slice to operate in one of the following modes:

BYPASSA register slice is not instantiated on the AXI channel.
FORWARDThe forward register slice inserts 1 clk cycle of latency and provides timing isolation in only the forward direction, that is, the valid signal and the payload of that AXI channel.
REVERSEThe reverse register slice inserts 0-1 clk cycle of latency and provides timing isolation in only the reverse direction, that is, the ready signal and the payload of that AXI channel.
FULLThe full register slice inserts 1-2 clk cycles of latency and provides timing isolation in the forward and reverse directions.

Latency calculations for read transfers

If no register slices are enabled, then the bridge can potentially perform read transfers with no added latency. If all registering is enabled the read latency is 4-6 clk cycles, depending on whether the connected slave has arready and rready HIGH.

When there are no added wait states, the read latency is:

  • read_latency = AHB_REG_CNTRL + lat(AXI_AR) + lat(AXI_R) + AHB_REG_RDATA

Wait states occur when the slave is not ready or the read data is delayed.

Latency calculations for write transfers

A write transfer can only have zero latency if the bridge can provide an early write response. Otherwise, the AXI protocol requires that the B channel write response must always follow the last W channel write transfer, which results in one extra clk cycle.

The AW channel latency is excluded, because it does not delay the write data channel.

If the bridge can provide an early write response, then for a single beat write the latency is:

  • write_latency_ewr = AHB_REG_CNTRL + AHB_REG_WDATA + lat(AXI_W) + AHB_REG_RDATA

If the bridge cannot provide an early write response, the latency is:

  • write_latency_noewr_last = AHB_REG_CNTRL + AHB_REG_WDATA + lat(AXI_W) +1 + lat(AXI_B) + AHB_REG_RDATA

If all registering is enabled on both AHB and AXI, then the minimum write latency is 6 clk cycles (5 wait states are inserted). The maximum write latency is 8 clk cycles.

Non-Confidential - BetaPDF file icon PDF version101375_0000_00_en
Copyright © 2018 Arm Limited or its affiliates. All rights reserved.