2.12 Response scheduling, response FIFO

The AXI5 to AHB5 bridge contains AXI response FIFOs for the R and B channels, because the AHB master cannot extend the AHB data phases. After the bridge issues the AHB address phase, the bridge must be able to store the incoming AHB data phase response in the next clk cycle, even if the destination AXI channel is unavailable (rready or bready is LOW). The response FIFO depth depends on the presence of AHB register slices.

The bridge accepts incoming AXI transactions only when the AHB slave interface is ready to accept or provide data (hready is HIGH) and the AXI response channel FIFO is ready to accept data. If either of these conditions is not met, the bridge stalls burst propagation by setting the respective axready, wready, rvalid, or bvalid signal LOW.

For an AXI write transaction, the bridge must provide a single write response. However, for AHB writes, the bridge receives a write response for each AHB beat. Therefore, the bridge accumulates all the write beat responses, belonging to the burst, and returns the most serious response (SLVERR > OKAY > HEXOKAY).

For an AXI read transaction, the bridge provides the response with each AHB beat. However, when the bridge splits up the first beat of an unaligned access, then the bridge accumulates all the read beat responses, belonging to the burst, and returns the most serious response (SLVERR > OKAY > HEXOKAY).

AXI transaction responses

The rresp and bresp signals convey the transaction response for the R channel and B channel, respectively. To generate the response, the bridge uses the AHB slave response and the internal bridge error state. An internal bridge error occurs when either:

  • The bridge receives an unsupported single, sparse Exclusive write transaction.
  • The bridge detects inconsistent use of the awsparse signal. For example, if awsparse is LOW and a write strobe bit, wstrb[(DATA_WIDTH/8)−1:0], is LOW.

If an internal bridge error occurs, then the bridge still propagates the transaction to the AHB interface and then it issues an SLVERR response on the bresp signal.


Inconsistent use of the awsparse signal might cause memory corruption.

For AXI transactions that translate to Non-exclusive AHB accesses, the AXI response is either OKAY or SLVERR. The SLVERR response can originate either from the AHB slave or the bridge.

For AXI transactions that translate to Exclusive AHB accesses, the AXI response can be EXOKAY, OKAY (which indicates an Exclusive fail), or SLVERR. In this case, all responses originate from the AHB slave signals hresp and hexokay.

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