Arm® Neoverse™ N1 System Development Platform Technical Reference Manual

Table of Contents

About this book
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1 Introduction
1.1 Precautions
1.1.1 Ensuring safety
1.1.2 Operating temperature
1.1.3 Preventing damage
1.2 About the N1 SDP
1.3 The N1 SDP at a glance
1.4 Getting started
2 Hardware description
2.1 N1 SDP hardware
2.2 N1 SoC
2.3 External power
2.3.1 Overview of power scheme
2.3.2 Power islands
2.4 Clocks
2.4.1 Overview of clocks
2.4.2 SoC clocks
2.4.3 Clock programming and control
2.4.4 IOFPGA clocks
2.5 Resets
2.6.1 Overview of IOFPGA
2.6.2 IOFPGA interrupts
2.7 HDLCD video
2.8 PCI Express and CCIX systems
2.8.1 Overview of PCIe and CCIX systems
2.8.2 PCI Express and CCIX expansion slots
2.8.3 SATA 3.0 ports
2.8.4 Gigabit Ethernet port
2.8.5 USB 3.0 ports
2.9 Chip to Chip communications
2.10 UARTs
2.11 LEDs, switches, and buttons
2.11.1 MCC system LEDs
2.11.2 PCC system LEDs
2.11.3 IOFPGA LEDs
2.11.4 Miscellaneous LEDs
2.11.5 Push buttons and switches
2.12 Debug
3 Configuration
3.1 Overview of the configuration process
3.2 Powerup and powerdown sequences
3.3 Configuration files
3.3.1 Overview of configuration files and microSD card directory structure
3.3.2 config.txt board configuration file
3.3.3 Contents of the MB directory
3.3.4 Contents of the SOFTWARE subdirectory
3.4 Configuration switches
3.4.1 Use of configuration switches
3.4.2 Remote UART configuration
3.5 Use of reset push buttons
3.6 Command-line interface
3.6.1 Overview of the N1 SDP MCC command-line interface
3.6.2 MCC main command menu
3.6.3 MCC debug menu
3.6.4 EEPROM menu
4 Programmers model
4.1 About this programmers model
4.2 N1 SDP memory maps
4.2.1 Application Processor memory map
4.2.2 Application Processor subsystem peripherals memory map
4.2.3 Manageability Control Processor memory map
4.2.4 Manageability Control Processor peripherals memory map
4.2.5 System Control Processor memory map
4.2.6 System Control Processor peripherals memory map
4.2.7 CoreSight™ system memory map
4.2.8 IOFPGA memory map
4.3 N1 SoC interrupt maps
4.3.1 Application Processor interrupt map
4.3.2 System Control Processor interrupt map
4.3.3 Manageability Control Processor interrupt map
4.4 System Security Control registers
4.4.1 System Security Control registers summary
4.4.2 SSC_DBGCFG_STAT Register
4.4.3 SSC_DBGCFG _SET Register
4.4.4 SSC_DBGCFG _CLR Register
4.4.5 SSC_AUXDBGCFG Register
4.4.6 SSC_GPRETN Register
4.4.7 SSC_VERSION Register
4.4.8 SSC_SW_SCRATCH Registers
4.4.9 SSC_SW_CAP Registers
4.4.10 SSC_SW_CAPCTRL Register
4.4.11 SSC_CHIPID_ST Register
4.4.12 PID4 Register
4.4.13 PID0 Register
4.4.14 PID1 Register
4.4.15 PID2 Register
4.4.16 COMPID0 Register
4.4.17 COMPID1 Register
4.4.18 COMPID2 Register
4.4.19 COMPID3 Register
4.5 Serial Configuration Control registers
4.5.1 Serial Configuration Control registers summary
4.5.2 PMCLK_DIV Register
4.5.3 SYSAPBCLK_CTRL Register
4.5.4 SYSAPBCLK _DIV Register
4.5.9 SCPNICCLK_CTRL Register
4.5.10 SCPNICCLK_DIV Register
4.5.11 SCPI2CCLK_CTRL Register
4.5.12 SCPI2CCLK_DIV Register
4.5.13 SCPQSPICLK_CTRL Register
4.5.14 SCPQSPICLK_DIV Register
4.5.15 SENSORCLK_CTRL Register
4.5.16 SENSORCLK_DIV Register
4.5.17 MCPNICCLK_CTRL Register
4.5.18 MCPNICCLK_DIV Register
4.5.19 MCPI2CCLK_CTRL Register
4.5.20 MCPI2CCLK_DIV Register
4.5.21 MCPQSPICLK_CTRL Register
4.5.22 MCPQSPICLK_DIV Register
4.5.23 PCIEAXICLK_CTRL Register
4.5.24 PCIEAXICLK_DIV Register
4.5.25 CCIXAXICLK_CTRL Register
4.5.26 CCIXAXICLK_DIV Register
4.5.27 PCIEAPBCLK_CTRL Register
4.5.28 PCIEAPBCLK_DIV Register
4.5.29 CCIXAPBCLK_CTRL Register
4.5.30 CCIXAPBCLK_DIV Register
4.5.31 SYS_CLK_EN Register
4.5.32 CPU0_PLL_CTRL0 Register
4.5.33 CPU0_PLL_CTRL1 Register
4.5.34 CPU1_PLL_CTRL0 Register
4.5.35 CPU1_PLL_CTRL1 Register
4.5.36 CLUS_PLL_CTRL0 Register
4.5.37 CLUS_PLL_CTRL1 Register
4.5.38 SYS_PLL_CTRL0 Register
4.5.39 SYS_PLL_CTRL1 Register
4.5.40 DMC_PLL_CTRL0 Register
4.5.41 DMC_PLL_CTRL1 Register
4.5.42 INT_PLL_CTRL0 Register
4.5.43 INT_PLL_CTRL1 Register
4.5.44 SYS_MAN_RESET Register
4.5.45 BOOT_CTL Register
4.5.46 BOOT_CTRL_STA Register
4.5.47 SCP_BOOT_ADR Register
4.5.48 MCP_BOOT_ADR Register
4.5.49 PLATFORM_CTRL Register
4.5.50 TARGETIDAPP Register
4.5.51 TARGETIDSCP Register
4.5.52 TARGETIDMCP Register
4.5.53 BOOT_GPR0 Register
4.5.54 BOOT_GPR1 Register
4.5.55 BOOT_GPR2 Register
4.5.56 BOOT_GPR3 Register
4.5.57 BOOT_GPR4 Register
4.5.58 BOOT_GPR5 Register
4.5.59 BOOT_GPR6 Register
4.5.60 BOOT_GPR7 Register
4.5.61 INSTANCE_ID Register
4.5.62 PCIE_BOOT_CTRL Register
4.5.63 DBG_AUTHN_CTRL Register
4.5.64 CTI0_CTRL Register
4.5.65 CTI1_CTRL Register
4.5.66 CTI0TO3_CTRL Register
4.5.67 MCP_WDOGCTI_CTRL Register
4.5.68 SCP_WDOGCTI_CTRL Register
4.5.69 DBGEXPCTI_CTRL Register
4.5.70 PCIE_PM_CTRL Register
4.5.71 CCIX_PM_CTRL Register
4.5.72 SCDBG_CTRL Register
4.5.73 EXP_IF_CTRL Register
4.5.74 RO_CTRL Register
4.5.75 CMN_CCIX_CTRL Register
4.5.76 STM_CTRL Register
4.5.77 AXI_OVRD_PCIE Register
4.5.78 AXI_OVRD_CCIX Register
4.5.79 AXI_OVRD_TSIF Register
4.5.80 TRACE_PAD_CTRL0 Register
4.5.81 TRACE_PAD_CTRL1 Register
4.5.82 IOFPGA_TMIF_PAD_CTRL Register
4.5.83 IOFPGA_TSIF_PAD_CTRL Register
4.5.84 APB_CTRL_CLR Register
4.5.85 PID4 Register
4.5.86 PID0 Register
4.5.87 PID1 Register
4.5.88 PID2 Register
4.5.89 PID3 Register
4.5.90 CID0 Register
4.5.91 CID1 Register
4.5.92 CID2 Register
4.5.93 CID3 Register
4.6 APB system registers
4.6.1 APB system register summary
4.6.2 SYS_ID Register
4.6.3 SYS_SW Register
4.6.4 SYS_LED Register
4.6.5 SYS_100HZ Register
4.6.6 SYS_FLAG Registers
4.6.7 SYS_CFGSW Register
4.6.8 SYS_24MHZ Register
4.6.9 SYS_PCIE_CNTL Register
4.6.10 SYS_PCIE_GBE Register
4.6.11 SYS_PROC_ID0 Register
4.6.12 SYS_FAN_SPEED Register
4.6.13 SP810_CTRL Register
4.7 APB energy meter registers
4.7.1 APB energy meter registers summary
4.7.2 SYS_I_SYS Register
4.7.3 SYS_I_CL0 Register
4.7.4 SYS_I_PCIE Register
4.7.5 SYS_I_CL1 Register
4.7.6 SYS_V_SYS Register
4.7.7 SYS_V_CL0 Register
4.7.8 SYS_V_PCIE Register
4.7.9 SYS_V_CL1 Register
4.7.10 SYS_POW_SYS Register
4.7.11 SYS_POW_CL0 Register
4.7.12 SYS_POW_PCIE Register
4.7.13 SYS_POW_CL1 Register
4.7.14 SYS_ENM_SYS Register
4.7.15 SYS_ENM_CL0 Register
4.7.16 SYS_ENM_PCIE Register
4.7.17 SYS_ENM_CL1 Register
4.7.18 SYS_I_DDR0 Register
4.7.19 SYS_I_DDR1 Register
4.7.20 SYS_V_DDR0 Register
4.7.21 SYS_V_DDR1 Register
4.7.22 SYS_POW_DDR0 Register
4.7.23 SYS_POW_DDR1 Register
4.7.24 SYS_ENM_DDR0 Register
4.7.25 SYS_ENM_DDR1 Register
4.8 UART memory addresses and control registers
A Signal descriptions
A.1 UART headers
A.2 UART DB9 connectors
A.3 N1-SoC JTAG connector
A.4 Trace connector
A.5 Front panel I/O header
A.6 PCI Express and CCIX slots
A.7 C2C connector
A.8 Power connectors
B Revisions
B.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-00 01 March 2019 Confidential Alpha1 release
0000-01 17 September 2019 Non-Confidential Alpha2 release.

Non-Confidential Proprietary Notice

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to.

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Product Status

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Web Address

Conformance Notices

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

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The system should be powered down when not in use.

It is recommended that ESD precautions be taken when handling development boards.

The board generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. There is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • Ensure attached cables do not lie across the target board.
  • Reorient the receiving antenna.
  • Increase the distance between the equipment and the receiver.
  • Connect the equipment into an outlet on a different circuit from the receiver.
  • Consult the dealer or an experienced radio/TV technician for help.


It is recommended that, wherever possible, shielded interface cables be used.
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