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The Peripheral Protection Controller (PPC) provides security checks for AXI peripherals.
The PPC gates AXI transactions towards a peripheral when a security violation occurs. It can be instantiated in the system in connection to any non-security aware AXI5 peripheral. Security checking is performed against the state of the cfg_ap and cfg_nonsec signals, which indicate the privilege and Security state of the peripheral.
The following figure shows the PPC interfaces.
The AXI slave and AXI master interfaces provide the AXI data path from the AXI master to the attached peripheral.
To support low-power quiescence, the PPC has two Q-Channel interfaces. One Q-Channel is for clock quiescence and the other Q-Channel is for power quiescence.
The cfg_nonsec signal controls the security settings of the attached peripheral:
The cfg_ap signal controls the privilege settings of the attached peripheral:
When the PPC blocks a transaction, the cfg_sec_resp signal controls whether the PPC: