7.3.8 Interrupt signal enable register, IRQ_EN

The IRQ_EN register controls whether the interrupt output signal, irq, is enabled.

Usage constraintsAccessible only from Secure state.
ConfigurationsAvailable in all configurations.
AttributesSee 7.2 Register summary.

The following figure shows the bit assignments.

Figure 7-8 IRQ_EN bit assignments
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The following table shows the bit assignments.

Table 7-9 IRQ_EN bit assignments

Bits Name Default Description
[31:1] - - Reserved, RAZ/WI.
[0] IRQ_EN 0

This bit controls whether the MPC can set irq HIGH when a security violation occurs:

0 = The interrupt output is disabled, so the irq signal is always LOW. Use this setting, if software detects interrupts by polling the IRQ_STAT register.

1 = The interrupt output is enabled. Use this setting, if an interrupt controller notifies the software when an interrupt occurs.

Note:

The irq_enable_rd and irq_enable_wr signals can prevent the MPC from setting the irq signal HIGH. See 3.3 MPC interrupts.
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