|Home > Programmers model > Register descriptions > Interrupt information register 1, IRQ_INFO1|
The IRQ_INFO1 register returns the address of the AXI transaction that triggered the security violation interrupt.
|Usage constraints||Accessible only from Secure state.|
|Configurations||Available in all configurations.|
|Attributes||See 7.2 Register summary.|
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 7-10 IRQ_INFO1 bit assignments
|[31:ADDR_WIDTH]||-||-||Reserved, RAZ. This field is not present when ADDR_WIDTH == 32.|
|[ADDR_WIDTH – 1:0]||FIRST_ADDR||0||
Returns the address of the security violation that triggered the interrupt and set IRQ_STAT.IRQ.STAT = 1.
When IRQ_STAT.IRQ.STAT == 1, if subsequent security violations occur, then the MPC does not update this field.