|Home > MPC functional description > About the MPC|
The Memory Protection Controller (MPC) acts as security gate for AXI transactions that target a memory interface. The security checks operate on block or page level, and are programmable by using the APB slave interface.
The following figure shows the MPC interfaces.
The AXI slave and AXI master interfaces provide the AXI data path from the interconnect to the memory controller.
To support low-power quiescence, the MPC has two Q-Channel interfaces. One Q-Channel is for clock quiescence and the other Q-Channel is for power quiescence.
At powerup, the MPC uses the value of the cfg_init_value input as the initialization value for the Look Up Table (LUT) to be Secure or Non-secure for the entire memory range that the MPC protects.
If a security violation occurs, the MPC generates an interrupt and the cfg_sec_resp controls whether the MPC: