|Home > ACG, SDB, and SUB functional description > Bridge upstream Q-Channels|
The upstream side of each bridge component provides three Q-Channel interfaces for power, clock, and external gate control.
Each Q-Channel implements the low-power interfaces that the AMBA® Low Power Interface Specification, Arm® Q-Channel and P-Channel Interfaces describes.
The power Q-Channel and clock Q-Channel implement a full Q-Channel interface. These interfaces enable the upstream side of the bridge to indicate when it requires clock and power.
The external-gating interface implements a partial Q-Channel interface that omits the QDENY and QACTIVE signals.
The presence of a synchronizer on the QREQn input of a Q-Channel is configurable. See the Arm® CoreLink™ SIE-300 AXI5 System IP for Embedded Configuration and Integration Manual for more information.