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Home > Signal descriptions > Bridge components signals > Bridge upstream signals |
The upstream side of each bridge component (ACG, SDB, or SUB) has an AXI5 slave interface. Bridge components also have an external-gating interface, two configuration signals, and two Q-Channel device interfaces.
The following tables list the clock and reset signals for the upstream side of each bridge component.
Table A-34 ACG upstream clock and reset signals
Signal | Direction | Description |
---|---|---|
aclk_s | Input | Clock |
aresetn_s | Input | Active-LOW reset. Reset can go LOW asynchronously but must go HIGH synchronously. |
Table A-35 SDB upstream clock and reset signals
Signal | Direction | Description |
---|---|---|
aclk_s | Input | Clock |
aresetn_s | Input | Active-LOW reset. Reset can go LOW asynchronously but must go HIGH synchronously. |
aclk_en_s | Input | Clock enable signal that enables the AXI5 slave interface to operate at either:
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Table A-36 SUB upstream clock and reset signals
Signal | Direction | Description |
---|---|---|
aclk_s | Input | Clock |
aresetn_s | Input | Active-LOW reset. Reset can go LOW asynchronously but must go HIGH synchronously. |
The following table lists the AXI5 slave interface signals.
Table A-37 Bridge upstream AXI5 slave interface signals
Signal | Direction | Description |
---|---|---|
AW channel signals: | ||
awvalid_s | Input | Write address valid signal. |
awaddr_s[ADDR_WIDTH−1:0] | Input | Write address signal. |
awburst_s[1:0] | Input | Write burst type signal. |
awid_s[ID_WIDTH−1:0] | Input | Write request ID signal. |
awlen_s[7:0] | Input | Write burst length signal. |
awsize_s[2:0] | Input | Write burst size signal. |
awlock_s | Input | Write lock type signal. |
awprot_s[2:0] | Input | Write protection type signal. |
awready_s | Output | Write address ready signal. |
awcache_s[3:0] | Input | Indicates how transactions are required to progress through a system. |
awqos_s[3:0] | Input | QoS identifier. |
awregion_s[3:0] | Input | Permits a single physical interface on a slave to be used for multiple logical interfaces. |
awuser_s[AWUSER_WIDTH−1:0] | Input | Write address channel User signal. |
AR channel signals: | ||
arvalid_s | Input | Read address valid signal. |
araddr_s[ADDR_WIDTH−1:0] | Input | Read address signal. |
arburst_s[1:0] | Input | Read burst type signal. |
arid_s[ID_WIDTH−1:0] | Input | Read request ID signal. |
arlen_s[7:0] | Input | Read address burst length signal. |
arsize_s[2:0] | Input | Read burst size signal. |
arlock_s | Input | Read lock type signal. |
arprot_s[2:0] | Input | Read protection type signal. |
arready_s | Output | Read address ready signal. |
arcache_s[3:0] | Input | Indicates how transactions are required to progress through a system. |
arqos_s[3:0] | Input | QoS identifier. |
arregion_s[3:0] | Input | Permits a single physical interface on a slave to be used for multiple logical interfaces. |
aruser_s[ARUSER_WIDTH−1:0] | Input | Read address channel User signal. |
W channel signals: | ||
wvalid_s | Input | Write data valid signal. |
wlast_s | Input | Indicates last transfer in a write burst. |
wstrb_s[(DATA_WIDTH/8)−1:0] | Input | Write byte lane strobes. |
wdata_s[DATA_WIDTH−1:0] | Input | Write data signal. |
wpoison_s[(DATA_WIDTH−1)/64:0] | Input | 64-bit data granule corruption indicator. |
wuser_s[WUSER_WIDTH−1:0] | Input | Write data User signal. |
wready_s | Output | Write data ready signal. |
R channel signals: | ||
rvalid_s | Output | Read data valid signal. |
rid_s[ID_WIDTH−1:0] | Output | Read data ID. |
rlast_s | Output | Indicates last transfer in read data. |
rdata_s[DATA_WIDTH−1:0] | Output | Read data. |
rresp_s[1:0] | Output | Read data response. |
rready_s | Input | Read data ready signal. |
ruser_s[RUSER_WIDTH−1:0] | Output | Read data User signal. |
rpoison_s[(DATA_WIDTH−1)/64:0] | Output | 64-bit data granule corruption indicator. |
B channel signals: | ||
bvalid_s | Output | Write response valid signal. |
bid_s[ID_WIDTH−1:0] | Output | Write response ID signal. |
buser_s[BUSER_WIDTH−1:0] | Output | Write response User signal. |
bresp_s[1:0] | Output | Write response signal. |
bready_s | Input | Write response ready signal. |
The following table lists the wakeup signals.
Table A-38 Bridge upstream wakeup signals
Signal | Direction | Description |
---|---|---|
awakeup_s | Input | When this signal is HIGH, it indicates that the AXI master is initiating activity on this interface. |
pwr_wake_qactive_m | Output | A wakeup indication towards the downstream PPU. The PPU can then wake up the downstream side of the bridge by driving the pwr_qreqn_m signal. |
The following table lists the external gating configuration signals.
Table A-39 Bridge upstream external gating configuration signals
Signal | Direction | Description |
---|---|---|
cfg_gate_resp | Input |
Controls how the bridge component responds to AXI transactions, when the downstream side of the AXI5 bridge is in external gating or power quiescence. When cfg_gate_resp is: 0 = the bridge component stalls the transaction until the external gating and power quiescence on each side of the bridge is released. 1 = the bridge component responds with an ERROR response. You can change the value of cfg_gate_resp during operation. The bridge component samples cfg_gate_resp during the first clock cycle of an incoming transaction, when arvalid_s or awvalid_s is HIGH. Note:Do not tie cfg_gate_resp HIGH, otherwise the bridge becomes stuck in a closed state. |
cfg_ext_gt_err_resp | Input |
Controls how the bridge component responds to AXI transactions, when the upstream external gating is in quiescence. When cfg_ext_gt_err_resp is: 0 = no effect. The cfg_gate_resp value controls the response behavior. 1 = forced error response. The bridge component accepts all currently stalled transactions and responds with an ERROR response. You can change the value of cfg_ext_gt_err_resp during operation only when upstream external gating request is not asserted. The bridge component samples cfg_ext_gt_err_resp at the first clock cycle of upstream external gating quiescence, and is in effect only during upstream external gating quiescence. |
The following table lists the external-gating signals. See 6.6 External gating of the AXI interface (upstream) for more information.
Table A-40 Bridge upstream external gating signals
Signal | Direction | Description |
---|---|---|
ext_gt_qreqn_s | Input | This signal indicates when a controller issues an external-gating entry or exit request to the bridge component. |
ext_gt_qacceptn_s | Output | This signal indicates when the bridge component accepts the external gating request. |
The following table lists the Q-Channel device signals.
Table A-41 Bridge upstream Q-Channel signals
Signal | Direction | Description |
---|---|---|
Clock control Q-Channel device signals: | ||
clk_qreqn_s | Input | This signal indicates when the controller issues a quiescence entry or exit request to the bridge component. |
clk_qacceptn_s | Output | This signal indicates when the bridge component accepts the quiescence request. |
clk_qdeny_s | Output | This signal indicates when the bridge component denies the quiescence request. |
clk_qactive_s | Output | This signal indicates when the bridge component is active and also when it requests to exit from quiescence. |
Power control Q-Channel device signals: | ||
pwr_qreqn_s | Input | This signal indicates when the controller issues a quiescence entry or exit request to the bridge component. |
pwr_qacceptn_s | Output | This signal indicates when the bridge component accepts the quiescence request. |
pwr_qdeny_s | Output | This signal indicates when the bridge component denies the quiescence request. |
pwr_qactive_s | Output | This signal indicates when the bridge component is active and also when it requests to exit from quiescence. |