7.3.12 Identification registers

The MPC has some ID registers that are at the end of the 4KB memory region. Software can use these registers to discover which components are present in an SoC.

Peripheral ID register 4, PIDR4

The PIDR4 register returns byte[4] of the peripheral identifier. A debugger during system discovery can use the peripheral ID to discover which peripherals are in the system and the size of the programming register space.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 7.2 Register summary.

The following figure shows the bit assignments.

Figure 7-12 PIDR4 register bit assignments
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The following table shows the bit assignments.

Table 7-13 PIDR4

Bits Name Value Function
[31:8] - 0 Reserved.
[7:4] 4KB_COUNT 0x0 Indicates that the MPC registers occupy a single 4KB page.
[3:0] JEP106_CONT_CODE 0x4 Indicates how many Continuation Codes (0x7F) an Arm device requires. For identifying an Arm device or product, the Standard Manufacturer’s Identification Code specifies a requirement of four Continuation Codes.

Peripheral ID registers 5-7, PIDR5, PIDR6, PIDR7

The PIDR5, PIDR6, and PIDR7 registers return byte[7:5] of the peripheral identifier. These bytes are unallocated and they all return zero.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 7.2 Register summary.

The following figure shows the bit assignments.

Figure 7-13 PIDR5, PIDR6, PIDR7 bit assignments
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The following table shows the bit assignments.

Table 7-14 PIDR5, PIDR6, PIDR7 bit assignments

Bits Name Value Function
[31:0] - 0x0 Reserved.

Peripheral ID register 0, PIDR0

The PIDR0 register returns byte[0] of the peripheral identifier. A debugger during system discovery can use the peripheral ID to discover which peripherals are in the system.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 7.2 Register summary.

The following figure shows the bit assignments.

Figure 7-14 PIDR0 register bit assignments
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The following table shows the register bit assignments.

Table 7-15 PIDR0

Bits Name Value Function
[31:8] - 0 Reserved.
[7:0] PART_0 0x65 Part number, bits[7:0], for the MPC. See also PIDR1.PART_1. The MPC part number is 0x865.

Peripheral ID register 1, PIDR1

The PIDR1 register returns byte[1] of the peripheral identifier. A debugger during system discovery can use the peripheral ID to discover which peripherals are in the system.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 7.2 Register summary.

The following figure shows the bit assignments.

Figure 7-15 PIDR1 register bit assignments
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The following table shows the register bit assignments.

Table 7-16 PIDR1

Bits Name Value Function
[31:8] - 0 Reserved.
[7:4] DES_0 0xB The JEDEC JEP106 ID code [3:0], which identifies Arm as the designer of the MPC. See also PIDR2.DES_1 and the Standard Manufacturer’s Identification Code.
[3:0] PART_1 0x8 Part number, bits[11:8], for the MPC. See also PIDR0.PART_0. The MPC part number is 0x865.

Peripheral ID register 2, PIDR2

The PIDR2 register returns byte[2] of the peripheral identifier. A debugger during system discovery can use the peripheral ID to discover which peripherals are in the system and its rmpn revision status.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 7.2 Register summary.

The following figure shows the bit assignments.

Figure 7-16 PIDR2 register bit assignments
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The following table shows the register bit assignments.

Table 7-17 PIDR2

Bits Name Value Function
[31:8] - 0 Reserved.
[7:4] REVISION 0x0 Revision identifier for the MPC:
  • 0x0 = r0p0.

Note:

The revision status identifier for the MPC might differ from the SIE-300 revision status identifier.
[3] JEDEC 0b1 Returns 1, which indicates the use of a JEDEC-assigned ID value.
[2:0] DES_1 0b011 The JEDEC JEP106 ID code [6:4], which identifies Arm as the designer of the MPC. See also PIDR1.DES_0[3:0] and the Standard Manufacturer’s Identification Code.

Peripheral ID register 3, PIDR3

The PIDR3 register returns byte[3] of the peripheral identifier. A debugger during system discovery can use the peripheral ID to discover which peripherals are in the system and whether the peripheral has any modifications applied.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 7.2 Register summary.

The following figure shows the bit assignments.

Figure 7-17 PIDR3 register bit assignments
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The following table shows the register bit assignments.

Table 7-18 PIDR3

Bits Name Value Function
[31:8] - 0 Reserved.
[7:4] REVAND 0x0 A nonzero value indicates that Arm has approved the application of a post-manufacture metal layer fix to the MPC silicon.
[3:0] CMOD 0x0 Customer modification number. A nonzero value indicates that the customer has modified the MPC RTL, which might affect its behavior. Do not modify this field unless you have permission from Arm.

Component ID register 0, CIDR0

The CIDR0 register returns byte[0] of the component ID. A debugger during system discovery can use the component ID to discover that the peripheral contains a programmers register block.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 7.2 Register summary.

The following figure shows the bit assignments.

Figure 7-18 CIDR0 register bit assignments
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The following table shows the register bit assignments.

Table 7-19 CIDR0

Bits Name Value Function
[31:8] - 0 Reserved.
[7:0] PRMBL_0 0x0D Preamble[0]. Returns segment 1 of the component identification code.

Component ID register 1, CIDR1

The CIDR1 register returns byte[1] of the component ID. A debugger during system discovery can use the component ID to discover that the peripheral contains a programmers register block and which component class the MPC belongs to.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 7.2 Register summary.

The following figure shows the bit assignments.

Figure 7-19 CIDR1 register bit assignments
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The following table shows the register bit assignments.

Table 7-20 CIDR1

Bits Name Value Function
[31:8] - 0 Reserved.
[7:4] CLASS 0xF Component class. Returns 0xF, which indicates that the MPC belongs to the CoreLink™ family.
[3:0] PRMBL_1 0x0 Preamble[1]. Returns segment 2 of the component identification code.

Component ID register 2, CIDR2

The CIDR2 register returns byte[2] of the component ID. A debugger during system discovery can use the component ID to discover that the peripheral contains a programmers register block.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 7.2 Register summary.

The following figure shows the bit assignments.

Figure 7-20 CIDR2 register bit assignments
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The following table shows the register bit assignments.

Table 7-21 CIDR2

Bits Name Value Function
[31:8] - 0 Reserved.
[7:0] PRMBL_2 0x05 Preamble[2]. Returns segment 2 of the component identification code.

Component ID register 3, CIDR3

The CIDR3 register returns byte[3] of the component ID. A debugger during system discovery can use the component ID to discover that the peripheral contains a programmers register block.

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesSee 7.2 Register summary.

The following figure shows the bit assignments.

Figure 7-21 CIDR3 register bit assignments
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The following table shows the register bit assignments.

Table 7-22 CIDR3

Bits Name Value Function
[31:8] - 0 Reserved.
[7:0] PRMBL_3 0xB1 Preamble[3]. Returns segment 3 of the component identification code.
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