7.2 Register summary

The Memory Protection Controller (MPC) registers occupy a 4KB region.

The following table shows the MPC registers in offset order from the base memory address.

Table 7-1 MPC register summary

Offset Name Type Width Description
0x000 CTRL RW 32 7.3.1 Control register, CTRL.
0x004-0x00C   - - Reserved, RAZ/WI.
0x010 BLK_MAX RO 32 7.3.2 Block index maximum value register, BLK_MAX.
0x014 BLK_CFG RO 32 7.3.3 Block LUT configuration status register, BLK_CFG.
0x018 BLK_IDX RW 32 7.3.4 Block LUT index register, BLK_IDX.
0x01C BLK_LUT[n] RW 32 7.3.5 Block LUT register, BLK_LUT.
0x020 IRQ_STAT RO 32 7.3.6 Interrupt status register, IRQ_STAT.
0x024 IRQ_CLEAR WO 32 7.3.7 Interrupt clear register, IRQ_CLEAR.
0x028 IRQ_EN RW 32 7.3.8 Interrupt signal enable register, IRQ_EN.
0x02C IRQ_INFO1 RO 32 7.3.9 Interrupt information register 1, IRQ_INFO1.
0x030 IRQ_INFO2 RO 32 7.3.10 Interrupt information register 2, IRQ_INFO2.
0x034 IRQ_SET WO 32 7.3.11 Interrupt set register, IRQ_SET.
0x038-0xFCC - - - Reserved, RAZ/WI.
0xFD0 PIDR4 RO 32 Peripheral ID register 4, PIDR4.
0xFD4 PIDR5 RO 32 Peripheral ID registers 5-7, PIDR5, PIDR6, PIDR7.
0xFD8 PIDR6 RO 32
0xFDC PIDR7 RO 32
0xFE0 PIDR0 RO 32 Peripheral ID register 0, PIDR0.
0xFE4 PIDR1 RO 32 Peripheral ID register 1, PIDR1.
0xFE8 PIDR2 RO 32 Peripheral ID register 2, PIDR2.
0xFEC PIDR3 RO 32 Peripheral ID register 3, PIDR3.
0xFF0 CIDR0 RO 32 Component ID register 0, CIDR0.
0xFF4 CIDR1 RO 32 Component ID register 1, CIDR1.
0xFF8 CIDR2 RO 32 Component ID register 2, CIDR2.
0xFFC CIDR3 RO 32 Component ID register 3, CIDR3.
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