3.2 MPC configuration options
The MPC has design options that configure the memory block size, the widths of some AXI signals, and the presence of synchronization logic on the Q-Channel inputs. You can also configure the MPC to support the AXI transaction gating feature.
When implementing the MPC in an SoC, you can configure:
- The width of the AXI address bus, by using the ADDR_WIDTH parameter. The parameter can be set to a value from 12-32 inclusive.
- The width of the AXI data bus, by using the DATA_WIDTH parameter. The possible widths are 32, 64, 128, or 256 bits.
- The width of the ID signals on the AXI interfaces, by using the ID_WIDTH parameter. The parameter can be set to a value from 2-32 inclusive.
- The width of the User signals on each AXI channel, by using the ARUSER_WIDTH, AWUSER_WIDTH, BUSER_WIDTH, RUSER_WIDTH, and WUSER_WIDTH parameters. A parameter can be set to a value from 0-256 inclusive.
- The size of a memory block, by using the BLK_SIZE parameter. The block size can be 256 bytes to 1MB. See 7.3.3 Block LUT configuration status register, BLK_CFG for the possible values.
- The MPC to support the AXI transaction gating feature, by using the GATE_PRESENT parameter. See 7.4 Gating AXI transactions during register updates for more information.
- The presence of a synchronizer on the Q-Channel QREQn inputs. See 3.4 MPC Q-Channels.