|Home > ACG, SDB, and SUB functional description > External gating of the AXI interface (downstream)|
The downstream side of each bridge component has a Q-Channel device interface. An external device can use the Q-Channel interface to gate transactions on the AXI interface.
The external-gating interface is a Q-Channel implementation without the QDENY and QACTIVE signals.
If the downstream side of the bridge receives a gating request, that is ext_gt_qreqn_m goes LOW, then the bridge sets eg_on_i HIGH to notify the upstream side to stall any new incoming AXI transactions.
The bridge component accepts an external gating request when there is no ongoing transfer and its internal buffers are empty. After the bridge component sets ext_gt_qacceptn_m LOW, the system can apply the reset to the downstream side of the bridge without the risk of data loss.
If the bridge component receives a new AXI transaction while ext_gt_qreqn_m is LOW, then the cfg_gate_resp signal controls whether the bridge component: