5.2 SMC configuration options

The SMC has design options that configure the number of Exclusive Access Monitors, the FIFO depths, and whether the first cycle of an AXI read transaction can bypass an AXI channel buffer. There are also options to set the widths of some AXI signals, and the presence of synchronization logic on the Q-Channel inputs. You can also configure the SMC to support AXI data poisoning.

When implementing the SMC in an SoC, you can configure:

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