7.3.6 Interrupt status register, IRQ_STAT

The IRQ_STAT register returns the interrupt status.

Usage constraintsAccessible only from Secure state.
ConfigurationsAvailable in all configurations.
AttributesSee 7.2 Register summary.

The following figure shows the bit assignments.

Figure 7-6 IRQ_STAT bit assignments
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The following table shows the bit assignments.

Table 7-7 IRQ_STAT bit assignments

Bits Name Default Description
[31:1] - - Reserved, RAZ.
[0] IRQ_STAT 0

This bit returns the interrupt status:

0 = The security violation interrupt is inactive, so the irq signal is LOW.

1 = The security violation interrupt is active. If IRQ_EN.IRQ_EN == 1, then the irq signal is HIGH.

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