7.3.10 Interrupt information register 2, IRQ_INFO2

The IRQ_INFO2 register returns extra information about the AXI transaction that triggered the security violation interrupt. It also indicates the occurrence of multiple violations and coincident read and write security violations.

Usage constraintsAccessible only from Secure state.
ConfigurationsAvailable in all configurations.
AttributesSee 7.2 Register summary.

The following figure shows the bit assignments.

Figure 7-10 IRQ_INFO2 bit assignments
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The following table shows the bit assignments.

Table 7-11 IRQ_INFO2 bit assignments

Bits Name Default Description
[31] AxPROT 0

Returns the AxPROT[1] value of the AXI transaction that triggered the security violation interrupt:

0 = A Secure AXI transaction triggered the interrupt.

1 = A Non-secure AXI transaction triggered the interrupt.

[30:25] - - Reserved, RAZ.
[24] ERR_MULTI 0

Indicates whether multiple security violations have occurred since the MPC set IRQ_STAT.IRQ_STAT = 1:

0 = No more security violations have occurred since the interrupt was triggered.

1 = More security violations have occurred since the interrupt was triggered.

[23:21] - - Reserved, RAZ.
[20] ERR_BOTH 0

Indicates whether coincident read and write security violations triggered the interrupt:

0 = No coincident read and write security violations have occurred when the interrupt was triggered.

1 = Coincident read and write security violations have occurred when the interrupt was triggered.

[19:17] - - Reserved, RAZ.
[16] WnR 0

Indicates whether a read or write AXI transaction triggered the security violation interrupt:

0 = A read AXI transaction triggered the interrupt.

1 = A write AXI transaction triggered the interrupt.

[15:0] AxID 0x0000

Returns the ID of the AXI transaction that triggered the security violation interrupt. The field returns either:

  • The arid_s[ID_WIDTH−1:0] value, for a read transaction security violation.
  • The awid_s[ID_WIDTH−1:0] value, for write transaction security violation.

If ID_WIDTH < 16, then the MPC sets the unallocated upper field bits to zero.

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