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The Master Security Controller (MSC) acts as security gate for AXI transactions, and it can transform the security attribute.
The MSC enables AXI masters that are designed for A-class systems to be inserted into M-class systems. Since A-class and M-class systems handle security differently, the MSC can transform the security attributes of a transaction to satisfy the M-class requirements.
The following figure shows the MSC interfaces.
The AXI slave and AXI master interfaces provide the AXI data path from the AXI master to the interconnect.
To support low-power quiescence, the MSC has two Q-Channel interfaces. One Q-Channel is for clock quiescence and the other Q-Channel is for power quiescence.
The cfg_nonsec input tells the MSC whether the AXI5 master, which connects to its slave interface, is in the Secure state or the Non-secure state. The MSC uses this information to control whether it blocks a transaction from going downstream.
When the MSC blocks a transaction, the cfg_sec_resp controls whether the MSC:
The MSC has two Implementation Defined Attribution Unit IDAU interfaces that it uses to discover the Security state of an addressed region. One IDAU is for read transactions and the other IDAU is for write transactions.
When the MSC receives an AXI transaction, it accesses the corresponding IDAU and retrieves the Security state for that transaction address. Using this information, the incoming AXI access permissions (AxPROT), and the state of cfg_nonsec, the MSC can do one of the following: