5.1 About the SMC

The SRAM Memory Controller (SMC) is an AXI5 memory controller for static memory devices.

The SMC has the following features:


The SRAM controller primarily supports memory macros that the Arm® SRAM Compiler generates.

The following figure shows the SMC interfaces.

Figure 5-1 SMC interfaces
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To support low-power quiescence, the SMC has two Q-Channel device interfaces. One Q-Channel is for clock quiescence and the other Q-Channel is for power quiescence.

The SMC also provides a partial Q-Channel device interface to support external gating, which stops the SMC from starting any new transactions on the SRAM interface. See 5.4 External gating of the SRAM interface.

Early write response

The SMC buffers the write transactions and for non-exclusive writes it returns an early write response. If the write buffers become full, then the SMC does not return an early write response.

Read and write transaction scheduling

The AXI has separate buses for reads and writes, but the SRAM interface is a single bus for reads and writes. Therefore, the SMC must arbitrate between the AXI channels. The SMC performs arbitration between read and write bursts.

If the write buffers become full, then the arbitration scheme uses the QoS value of the incoming read, arqos, and write, awqos signal. For example, if the SMC receives a write with a QoS value that is higher than the read QoS, it forwards the oldest transaction from the write queue to the SRAM to allow the new write into the write buffer.


Provided the write buffers (address or data) are not full, the SMC gives priority to read bursts.

To prevent system livelock or starvation issues, the SMC uses a balancing counter to track how many read bursts are granted while a write burst request is present but not granted. If this counter reaches a predefined value, then the SMC grants the write at the next arbitration point, regardless of the QoS values.


The AXI5_POISON_EN configuration parameter controls whether the SMC supports data poisoning. When data poisoning is enabled, the SMC provides 1-bit of poison information for each 64-bit of data.

The following table lists which signals contain the poison information for different DATA_WIDTH configurations.

Table 5-1 Poison bit locations

DATA_WIDTH AXI poison bits Poison bits on the SRAM interface
32 wpoison[0] and rpoison[0] memd[32] and memq[32]
64 wpoison[0] and rpoison[0] memd[64] and memq[64]
128 wpoison[1:0] and rpoison[1:0] memd[129:128] and memq[129:128]
256 wpoison[3:0] and rpoison[3:0] memd[259:256] and memq[259:256]

Exclusive accesses

The SMC can contain up to 16 Exclusive Access Monitors (EAMs), depending on the setting of the EXCLUSIVE_MONITORS configuration parameter.

If EXCLUSIVE_MONITORS > 0, then Exclusive Load transactions always return an EXOKAY response and the SMC stores the transaction details (address, ID) in an internal TAG buffer.

For Exclusive Store transactions, the SMC checks if the address and ID are present in the TAG buffer, and if so the SMC forwards the write to the SRAM and returns an EXOKAY write response. If the check fails, the SMC ignores the write data and it returns an OKAY response, which indicates an exclusive access failure.

If a non-exclusive write transaction accesses a location that is stored in a TAG buffer, then the SMC clears the TAG.

If all EAMs are occupied, and the SMC receives a new Exclusive Load transaction with an:

  • ID that exists in the TAG table, then the new transaction replaces an old entry.
  • ID that does not exist in the TAG table, then the SMC overwrites an entry in the TAG table that the round-robin algorithm selects, and returns an EXOKAY response.

If an SMC is configured to contain no EAMs (EXCLUSIVE_MONITORS == 0), then exclusive writes always fail. The SMC ignores the write and returns an OKAY response.

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