2.3 MSC interrupts

The MSC has a level-sensitive interrupt output, irq, that can indicate the occurrence of a security violation or a faulty security attribute conversion.

For read transactions, the irq_enable_rd signal controls whether the MSC can set irq HIGH when a security violation or a faulty security attribute conversion occurs during a read transaction.

For write transactions, the irq_enable_wr signal controls whether the MSC can set irq HIGH when a security violation or a faulty security attribute conversion occurs during a write transaction.

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