1.1 About the AXI5 System IP for Embedded
The SIE-300 AXI5 System IP for Embedded provides a set of configurable AXI5 security-aware components. The components can protect peripherals and memories that are unaware of security, so that a peripheral or memory is only accessible to trusted software. The SIE-300 also provides clock synchronizing bridges and an access control gate.
The SIE-300 consists of the following components:
- Master Security Controller (MSC)
- The MSC acts as security gate for AXI transactions, and it can transform the security attribute.
- Memory Protection Controller (MPC)
- The MPC acts as security gate for AXI transactions that target a memory interface. The security checks operate on block or page level, and are programmable by using the APB slave interface.
- Peripheral Protection Controller (PPC)
- The PPC gates AXI5 transactions to, and responses from, peripherals when a security violation occurs.
- Access Control Gate (ACG)
- The ACG component can be placed on a clock or power domain boundary to pass or block AXI5 transactions whenever the downstream component cannot accept the transaction, or is explicitly asked not to do so. The transaction is latched internally and the ACG generates automatic responses when necessary.
- Sync-Down Bridge (SDB)
- The SDB synchronizes AXI5 interfaces where the upstream side is faster than the downstream side and the clocks are synchronous, in phase and have an N:1 frequency ratio.
- Sync-Up Bridge (SUB)
- The SUB synchronizes AXI5 interfaces where the upstream side is slower than the downstream side and the clocks are synchronous, in phase, and have a 1:N frequency ratio.
- SRAM Memory Controller (SMC)
- The SMC enables on-chip synchronous RAM blocks to attach to an AXI5 interface. The SMC supports 32, 64, 128, or 256-bit SRAM with byte writes.