7.3.7 Interrupt clear register, IRQ_CLEAR

The IRQ_CLEAR register clears the interrupt.

Usage constraintsAccessible only from Secure state.
ConfigurationsAvailable in all configurations.
AttributesSee 7.2 Register summary.

The following figure shows the bit assignments.

Figure 7-7 IRQ_CLEAR bit assignments
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The following table shows the bit assignments.

Table 7-8 IRQ_CLEAR bit assignments

Bits Name Default Description
[31:1] - - Reserved.

This bit clears the interrupt:

0 = The MPC ignores the write, so the interrupt state remains unchanged.

1 = The MPC clears the interrupt by:

  • Setting IRQ_STAT.IRQ_STAT = 0.
  • Setting IRQ_INFO2.ERR_MULTI = 0.
  • Setting the irq signal LOW.
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