A.4 SMC signals

The SRAM Memory Controller (SMC) has an AXI5 slave interface and an SRAM interface. The SMC also has an external-gating interface, configuration signal, and two Q-Channel device interfaces.

The following table lists the clock and reset signals.

Table A-27 SMC clock and reset signals

Signal Direction Description
aclk Input Clock
aresetn Input Active-LOW reset. Reset can go LOW asynchronously but must go HIGH synchronously.

The following table lists the AXI5 slave interface signals.

Table A-28 SMC AXI5 slave interface signals

Signal Direction Description
AW channel signals:
awvalid_s Input Write address valid signal.
awaddr_s[ADDR_WIDTH−1:0] Input Write address signal.
awburst_s[1:0] Input Write burst type signal.
awid_s[ID_WIDTH−1:0] Input Write request ID signal.
awlen_s[7:0] Input Write burst length signal.
awsize_s[2:0] Input Write burst size signal.
awlock_s Input Write lock type signal.
awprot_s[2:0] Input Write protection type signal.
awready_s Output Write address ready signal.
awqos_s[3:0] Input QoS identifier.
AR channel signals:
arvalid_s Input Read address valid signal.
araddr_s[ADDR_WIDTH−1:0] Input Read address signal.
arburst_s[1:0] Input Read burst type signal.
arid_s[ID_WIDTH−1:0] Input Read request ID signal.
arlen_s[7:0] Input Read address burst length signal.
arsize_s[2:0] Input Read burst size signal.
arlock_s Input Read lock type signal.
arprot_s[2:0] Input Read protection type signal.
arready_s Output Read address ready signal.
arqos_s[3:0] Input QoS identifier.
W channel signals:
wvalid_s Input Write data valid signal.
wlast_s Input Indicates last transfer in a write burst.
wstrb_s[(DATA_WIDTH/8)−1:0] Input Write byte lane strobes.
wdata_s[DATA_WIDTH−1:0] Input Write data signal.
wpoison_s[(DATA_WIDTH−1)/64:0] Input 64-bit data granule corruption indicator.
wready_s Output Write data ready signal.
R channel signals:
rvalid_s Output Read data valid signal.
rid_s[ID_WIDTH−1:0] Output Read data ID.
rlast_s Output Indicates last transfer in read data.
rdata_s[DATA_WIDTH−1:0] Output Read data.
rresp_s[1:0] Output Read data response.
rready_s Input Read data ready signal.
rpoison_s[(DATA_WIDTH−1)/64:0] Output 64-bit data granule corruption indicator.
B channel signals:
bvalid_s Output Write response valid signal.
bid_s[ID_WIDTH−1:0] Output Write response ID signal.
bresp_s[1:0] Output Write response signal.
bready_s Input Write response ready signal.

The following table lists the low-power signal on the AXI5 slave interface.

Table A-29 SMC AXI5 slave interface low-power signal

Signal Direction Description
awakeup Input When this signal is HIGH, it indicates that the AXI master is initiating activity on this interface.

The following table shows the SRAM master interface signals.

Note:

MDAT_WIDTH is a local variable rather than a configuration parameter, which represents the data width and the poison information. Therefore, MDAT_WIDTH is either:
  • DATA_WIDTH + (DATA_WIDTH−1)/64 + 1, when AXI5_POISON_EN=1.
  • DATA_WIDTH, when AXI5_POISON_EN=0.

Table A-30 SRAM master interface signals

Signal Direction Description
memaddr[ADDR_WIDTH−1:0] Output Address signal.
memd[MDAT_WIDTH−1:0] Output Write data signal.
memwen[(MDAT_WIDTH−1)/8:0] Output Byte write strobe signal.
memq[MDAT_WIDTH−1:0] Input Read data signal.
memcen Output Chip select signal.

The following table lists the external-gating configuration signal.

Table A-31 SMC external-gating configuration signal

Signal Direction Description
cfg_gate_resp Input

Controls how the SMC responds to AXI transactions, when an external device gates transactions on the SRAM interface. When cfg_gate_resp is:

0 = SMC stalls the transaction until the external gating is released.

1 = SMC responds with an ERROR response.

You can change the value of the cfg_gate_resp during operation. The SMC samples cfg_gate_resp as it enters the externally gated state.

The following table lists the external gating signals. See 5.4 External gating of the SRAM interface for more information.

Table A-32 SMC external gating signals

Signal Direction Description
ext_gt_qreqn Input This signal indicates when the controller issues an external-gating entry or exit request to the SMC.
ext_gt_qacceptn Output This signal indicates when the SMC accepts the external gating request.

The following table lists the Q-Channel device signals.

Table A-33 Q-Channel signals for the SMC

Signal Direction Description
Clock control Q-Channel device signals:
clk_qreqn Input This signal indicates when the controller issues a quiescence entry or exit request to the SMC.
clk_qacceptn Output This signal indicates when the SMC accepts the quiescence request.
clk_qdeny Output This signal indicates when the SMC denies the quiescence request.
clk_qactive Output This signal indicates when the SMC is active and also when it requests to exit from quiescence.
Power control Q-Channel device signals:
pwr_qreqn Input This signal indicates when the controller issues a quiescence entry or exit request to the SMC.
pwr_qacceptn Output This signal indicates when the SMC accepts the quiescence request.
pwr_qdeny Output This signal indicates when the SMC denies the quiescence request.
pwr_qactive Output This signal indicates when the SMC is active and also when it requests to exit from quiescence.
Non-ConfidentialPDF file icon PDF version101526_0100_02_en
Copyright © 2019 Arm Limited or its affiliates. All rights reserved.