Arm CoreLink SIE-300 AXI5 System IP for Embedded Technical Reference Manual : A.5.2 Bridge downstream signals

A.5.2 Bridge downstream signals

The downstream side of each bridge component (ACG, SDB, or SUB) has an AXI5 master interface and an SRAM interface. Bridge components also have an external-gating interface, a configuration signal, and two Q-Channel device interfaces.

The following tables list the clock and reset signals for the downstream side of each bridge component.

Table A-42 ACG downstream clock and reset signals

Signal	Direction	Description
aclk_m	Input	Clock
aresetn_m	Input	Active-LOW reset. Reset can go LOW asynchronously but must go HIGH synchronously.

Table A-43 SDB downstream clock and reset signals

Signal	Direction	Description
aclk_m	Input	Clock
aresetn_m	Input	Active-LOW reset. Reset can go LOW asynchronously but must go HIGH synchronously.

Table A-44 SUB downstream clock and reset signals

Signal	Direction	Description
aclk_m	Input	Clock
aresetn_m	Input	Active-LOW reset. Reset can go LOW asynchronously but must go HIGH synchronously.
aclk_en_m	Input	Clock enable signal that enables the AXI5 slave interface to operate at either: The aclk_m frequency. A divided integer multiple of aclk_m that is aligned to aclk_m.

The following table lists the AXI5 master interface signals.

Table A-45 Bridge downstream AXI5 master interface signals

Signal	Direction	Description
AW channel signals:
awvalid_m	Output	Write address valid signal.
awaddr_m[ADDR_WIDTH−1:0]	Output	Write address signal.
awburst_m[1:0]	Output	Write burst type signal.
awid_m[ID_WIDTH−1:0]	Output	Write request ID signal.
awlen_m[7:0]	Output	Write burst length signal.
awsize_m[2:0]	Output	Write burst size signal.
awlock_m	Output	Write lock type signal.
awprot_m[2:0]	Output	Write protection type signal.
awready_m	Input	Write address ready signal.
awcache_m[3:0]	Output	Indicates how transactions are required to progress through a system.
awqos_m[3:0]	Output	QoS identifier.
awregion_m[3:0]	Output	Permits a single physical interface on a slave to be used for multiple logical interfaces.
awuser_m[AWUSER_WIDTH−1:0]	Output	Write address channel User signal.
AR channel signals:
arvalid_m	Output	Read address valid signal.
araddr_m[ADDR_WIDTH−1:0]	Output	Read address signal.
arburst_m[1:0]	Output	Read burst type signal.
arid_m[ID_WIDTH−1:0]	Output	Read request ID signal.
arlen_m[7:0]	Output	Read address burst length signal.
arsize_m[2:0]	Output	Read burst size signal.
arlock_m	Output	Read lock type signal.
arprot_m[2:0]	Output	Read protection type signal.
arcache_m[3:0]	Output	Indicates how transactions are required to progress through a system.
arqos_m[3:0]	Output	QoS identifier.
arregion_m[3:0]	Output	Permits a single physical interface on a slave to be used for multiple logical interfaces.
aruser_m[ARUSER_WIDTH−1:0]	Output	Read address channel User signal.
W channel signals:
wvalid_m	Output	Write data valid signal.
wlast_m	Output	Indicates last transfer in a write burst.
wstrb_m[(DATA_WIDTH/8)−1:0]	Output	Write byte lane strobes.
wdata_m[DATA_WIDTH−1:0]	Output	Write data signal.
wpoison_m[(DATA_WIDTH−1)/64:0]	Output	64-bit data granule corruption indicator.
wuser_m[WUSER_WIDTH−1:0]	Output	User-defined signal.
wready_m	Input	Write data ready signal.
R channel signals:
rvalid_m	Output	Read data valid signal.
rid_m[ID_WIDTH−1:0]	Output	Read data ID.
rlast_m	Output	Indicates last transfer in read data.
rdata_m[DATA_WIDTH−1:0]	Output	Read data.
rresp_m[1:0]	Output	Read data response.
rready_m	Input	Read data ready signal.
ruser_m[RUSER_WIDTH−1:0]	Output	User-defined signal.
rpoison_m[(DATA_WIDTH−1)/64:0]	Input	64-bit data granule corruption indicator.
B channel signals:
bvalid_m	Input	Write response valid signal.
bid_m[ID_WIDTH−1:0]	Input	Write response ID signal.
buser_m[BUSER_WIDTH−1:0]	Input	Write response User signal.
bresp_m[1:0]	Input	Write response signal.
bready_m	Output	Write response ready signal.

The following table lists the low-power signal on the AXI5 slave interface.

Table A-46 Bridge downstream AXI5 master interface low-power signal

Signal	Direction	Description
awakeup_m	Output	When this signal is HIGH, it indicates that the bridge component is initiating activity on this interface.

The following table lists the external gating signals. See 6.7 External gating of the AXI interface (downstream) for more information.

Table A-47 Bridge downstream external gating signals

Signal	Direction	Description
ext_gt_qreqn_m	Input	This signal indicates when the controller issues an external-gating entry or exit request to the bridge component.
ext_gt_qacceptn_m	Output	This signal indicates when the bridge component accepts the external gating request.

The following table lists the Q-Channel device signals.

Table A-48 Bridge downstream Q-Channel signals

Signal	Direction	Description
Clock control Q-Channel device signals:
clk_qreqn_m	Input	This signal indicates when the controller issues a quiescence entry or exit request to the bridge component.
clk_qacceptn_m	Output	This signal indicates when the bridge component accepts the quiescence request.
clk_qdeny_m	Output	This signal indicates when the bridge component denies the quiescence request.
clk_qactive_m	Output	This signal indicates when the bridge component is active and also when it requests to exit from quiescence.
Power control Q-Channel device signals:
pwr_qreqn_m	Input	This signal indicates when the controller issues a quiescence entry or exit request to the bridge component.
pwr_qacceptn_m	Output	This signal indicates when the bridge component accepts the quiescence request.
pwr_qdeny_m	Output	This signal indicates when the bridge component denies the quiescence request.
pwr_qactive_m	Output	This signal indicates when the bridge component is active and also when it requests to exit from quiescence.

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