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Home > Signal descriptions > Bridge components signals > Intra-bridge signals |
The upstream and downstream sides of each bridge component (ACG, SDB, or SUB) communicate using intra-bridge interfaces. Each intra-bridge interface has an AXI5 interface, a Q-Channel device interface, two wakeup signals, and a gating signal.
The following table lists the AXI5 interface signals that connect the upstream side to the downstream side of the bridge component.
Table A-49 Intra-bridge AXI5 interface signals
Signal | Direction | Description |
---|---|---|
AW channel signals: | ||
awvalid_i | Upstream to downstream | Write address valid signal. |
awaddr_i[ADDR_WIDTH−1:0] | Upstream to downstream | Write address signal. |
awburst_i[1:0] | Upstream to downstream | Write burst type signal. |
awid_i[ID_WIDTH−1:0] | Upstream to downstream | Write request ID signal. |
awlen_i[7:0] | Upstream to downstream | Write burst length signal. |
awsize_i[2:0] | Upstream to downstream | Write burst size signal. |
awlock_i | Upstream to downstream | Write lock type signal. |
awprot_i[2:0] | Upstream to downstream | Write protection type signal. |
awready_i | Downstream to upstream | Write address ready signal. |
awcache_i[3:0] | Upstream to downstream | Indicates how transactions are required to progress through a system. |
awqos_i[3:0] | Upstream to downstream | QoS identifier. |
awregion_i[3:0] | Upstream to downstream | Permits a single physical interface on a slave to be used for multiple logical interfaces. |
awuser_i[AWUSER_WIDTH−1:0] | Upstream to downstream | Write address channel User signal. |
AR channel signals: | ||
arvalid_i | Upstream to downstream | Read address valid signal. |
araddr_i[ADDR_WIDTH−1:0] | Upstream to downstream | Read address signal. |
arburst_i[1:0] | Upstream to downstream | Read burst type signal. |
arid_i[ID_WIDTH−1:0] | Upstream to downstream | Read request ID signal. |
arlen_i[7:0] | Upstream to downstream | Read address burst length signal. |
arsize_i[2:0] | Upstream to downstream | Read burst size signal. |
arlock_i | Upstream to downstream | Read lock type signal. |
arprot_i[2:0] | Upstream to downstream | Read protection type signal. |
arready_i | Downstream to upstream | Read address ready signal. |
arcache_i[3:0] | Upstream to downstream | Indicates how transactions are required to progress through a system. |
arqos_i[3:0] | Upstream to downstream | QoS identifier. |
arregion_i[3:0] | Upstream to downstream | Permits a single physical interface on a slave to be used for multiple logical interfaces. |
aruser_i[ARUSER_WIDTH−1:0] | Upstream to downstream | Read address channel User signal. |
W channel signals: | ||
wvalid_i | Upstream to downstream | Write data valid signal. |
wlast_i | Upstream to downstream | Indicates last transfer in a write burst. |
wstrb_i[(DATA_WIDTH/8)−1:0] | Upstream to downstream | Write byte lane strobes. |
wdata_i[DATA_WIDTH−1:0] | Upstream to downstream | Write data signal. |
wpoison_i[(DATA_WIDTH−1)/64:0] | Upstream to downstream | 64-bit data granule corruption indicator. |
wuser_i[WUSER_WIDTH−1:0] | Upstream to downstream | Write data User signal. |
wready_i | Downstream to upstream | Write data ready signal. |
R channel signals: | ||
rvalid_i | Downstream to upstream | Read data valid signal. |
rid_i[ID_WIDTH−1:0] | Downstream to upstream | Read data ID. |
rlast_i | Downstream to upstream | Indicates last transfer in read data. |
rdata_i[DATA_WIDTH−1:0] | Downstream to upstream | Read data. |
rresp_i[1:0] | Downstream to upstream | Read data response. |
rready_i | Upstream to downstream | Read data ready signal. |
ruser_i[RUSER_WIDTH−1:0] | Downstream to upstream | Read data User signal. |
rpoison_i[(DATA_WIDTH−1)/64:0] | Downstream to upstream | 64-bit data granule corruption indicator. |
B channel signals: | ||
bvalid_i | Downstream to upstream | Write response valid signal. |
bid_i[ID_WIDTH−1:0] | Downstream to upstream | Write response ID signal. |
buser_i[BUSER_WIDTH−1:0] | Downstream to upstream | Write response User signal. |
bresp_i[1:0] | Downstream to upstream | Write response signal. |
bready_i | Upstream to downstream | Write response ready signal. |
The following table lists the intra-bridge wakeup signals.
Table A-50 Intra-bridge wakeup signals
Signal | Direction | Description |
---|---|---|
awakeup_i | Upstream to downstream | When this signal is HIGH, it indicates that the bridge is initiating activity on this interface. |
clk_wake_i | Upstream to downstream | Forwards a wakeup request for the clock to be active for the downstream side of the bridge. |
The following table lists the intra-bridge gating signals.
Table A-51 Intra-bridge gating signal
Signal | Direction | Description |
---|---|---|
eg_on_i | Downstream to upstream | This signal indicates when the downstream side of the bridge component receives an external gating request: 1 = The source of the intra-bridge quiescence request is an external gating request. The bridge cannot deny this request. 0 = The source of the intra-bridge quiescence request is not an external gating request. The bridge can deny the request. |
The following table lists the intra-bridge Q-Channel device signals.
Table A-52 Intra-bridge Q-Channel signals
Signal | Direction | Description |
---|---|---|
ib_qreqn_i | Downstream to upstream | This signal indicates when the downstream side of the bridge component issues a quiescence entry or exit request to the upstream side of the bridge component. |
ib_qacceptn_i | Upstream to downstream | This signal indicates when the bridge component accepts the quiescence request. |
ib_qdeny_i | Upstream to downstream | This signal indicates when the bridge component denies the quiescence request. |
ib_qactive_i | Upstream to downstream | This signal indicates when the bridge component is active and also when it requests to exit from quiescence. |