|Home > ACG, SDB, and SUB functional description > About the bridge components|
Bridge components provide low-power management and external gating on boundaries between clock and power domains along the AXI5 data bus. They also have configurable registering options to ease timing on long AXI5 paths.
The following figure shows the interfaces of a bridge component.
The following table lists the SIE-300 bridge components.
Table 6-1 Supported bridge components
|Bridge component||Upstream to downstream clock ratio|
|Access Control Gate (ACG)||One-to-one|
|Sync-Down Bridge (SDB)||N-to-one|
|Sync-Up Bridge (SUB)||One-to-N|
Each bridge component consists of an upstream side and a downstream side. To allow communication across clock and power domains, each side of the bridge has one intra-bridge Q-Channel interface and one intra-bridge AXI interface. The eg_on_i signal provides the upstream side with information about the state of external gating on the downstream side. The intra-bridge uses a standard Q-Channel LPI interface.
Each half of a bridge component supports the following features:
The cfg_gate_resp controls how the upstream side of the bridge component responds, when the bridge is closed by external gating or downstream power quiescence:
The cfg_ext_gt_err_resp signal controls how the bridge component responds to AXI transactions, when the upstream external gating is in quiescence. However, if the cfg_gate_resp is set to error, then the bridge returns an error response. Therefore, when the upstream external gating is in quiescence, the bridge: