3.3 MPC interrupts

The MPC has a level-sensitive interrupt output, irq, that can indicate the occurrence of a security violation.

If a security violation occurs when irq is LOW, the MPC saves information about the violation in the IRQ_STAT, IRQ_INFO1, and IRQ_INFO2 registers. Also, if the IRQ_EN register bit is set to 1 and the corresponding irq_enable_* signal is HIGH, then the MPC sets the irq interrupt HIGH. The irq signal remains HIGH until the IRQ_CLEAR register is written to.

Note:

  • If more security violations occur, then the MPC does not update the IRQ_STAT, IRQ_INFO1, and IRQ_INFO2 registers. However, if a security violation occurs while already in interrupt and irq_enable_* is set, then the MPC does update the IRQ_INFO2.ERR_MULTI bit.
  • When IRQ_EN.IRQ_EN == 0 and irq is LOW, if coincident violations occur for a read transaction and a write transaction, the MPC saves information about the read violation in the IRQ_STAT, IRQ_INFO1, and IRQ_INFO2 registers.

Disabling interrupts for memory accesses from a debugger

If the IRQ_SET register bit is set to 0, a debugger can use the irq_enable_* signals to prevent interrupt generation when it accesses memory regions. The irq_enable_rd signal controls whether the MPC can set irq HIGH when a security violation occurs during a read transaction. The irq_enable_wr signal controls whether the MPC can set irq HIGH when a security violation occurs during a write transaction.

Note:

If the IRQ_SET register bit is set to 1, then the MPC ignores the irq_enable_* signals and generates interrupts when IRQ_EN.IRQ_EN == 1.
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