A.1 MSC signals

The Master Security Controller (MSC) has an AXI5 slave interface and an AXI5 master interface. The MSC also has an Implementation Defined Attribution Unit IDAU-Lite interface, interrupts, configuration signals, and two Q-Channel device interfaces.

The following table lists the clock and reset signals.

Table A-1 MSC clock and reset signals

Signal Direction Description
aclk Input Clock
aresetn Input Active-LOW reset. Reset can go LOW asynchronously but must go HIGH synchronously.

The following table lists the AXI5 slave interface signals.

Table A-2 MSC AXI5 slave interface signals

Signal Direction Description
AW channel signals:
awvalid_s Input Write address valid signal.
awaddr_s[ADDR_WIDTH−1:0] Input Write address signal.
awburst_s[1:0] Input Write burst type signal.
awid_s[ID_WIDTH−1:0] Input Write request ID signal.
awlen_s[7:0] Input Write burst length signal.
awsize_s[2:0] Input Write burst size signal.
awlock_s Input Write lock type signal.
awprot_s[2:0] Input Write protection type signal.
awready_s Output Write address ready signal.
awcache_s[3:0] Input Indicates how transactions are required to progress through a system.
awregion_s[3:0] Input Permits a single physical interface on a slave to be used for multiple logical interfaces.
awqos_s[3:0] Input QoS identifier.
awuser_s[AWUSER_WIDTH−1:0] Input User-defined signal.
AR channel signals:
arvalid_s Input Read address valid signal.
araddr_s[ADDR_WIDTH−1:0] Input Read address signal.
arburst_s[1:0] Input Read burst type signal.
arid_s[ID_WIDTH−1:0] Input Read request ID signal.
arlen_s[7:0] Input Read address burst length signal.
arsize_s[2:0] Input Read burst size signal.
arlock_s Input Read lock type signal.
arprot_s[2:0] Input Read protection type signal.
arready_s Output Read address ready signal.
arcache_s[3:0] Input Indicates how transactions are required to progress through a system.
arregion_s[3:0] Input Permits a single physical interface on a slave to be used for multiple logical interfaces.
arqos_s[3:0] Input QoS identifier.
aruser_s[ARUSER_WIDTH−1:0] Input User-defined signal.
W channel signals:
wvalid_s Input Write data valid signal.
wlast_s Input Indicates last transfer in a write burst.
wstrb_s[(DATA_WIDTH/8)−1:0] Input Write byte lane strobes.
wdata_s[DATA_WIDTH−1:0] Input Write data signal.
wpoison_s[(DATA_WIDTH−1)/64:0] Input 64-bit data granule corruption indicator.
wuser_s[WUSER_WIDTH−1:0] Input User-defined signal.
wready_s Output Write data ready signal.
R channel signals:
rvalid_s Output Read data valid signal.
rid_s[ID_WIDTH−1:0] Output Read data ID.
rlast_s Output Indicates last transfer in read data.
rdata_s[DATA_WIDTH−1:0] Output Read data.
ruser_s[RUSER_WIDTH−1:0] Output User-defined signal.
rresp_s[1:0] Output Read data response.
rready_s Input Read data ready signal.
rpoison_s[(DATA_WIDTH−1)/64:0] Output 64-bit data granule corruption indicator.
B channel signals:
bvalid_s Output Write response valid signal.
bid_s[ID_WIDTH−1:0] Output Write response ID signal.
bresp_s[1:0] Output Write response signal.
bready_s Input Write response ready signal.
buser_s[BUSER_WIDTH−1:0] Output User-defined signal.

The following table lists the low-power signal on the AXI5 slave interface.

Table A-3 MSC AXI5 slave interface low-power signal

Signal Direction Description
awakeup_s Input When this signal is HIGH, it indicates that the AXI master is initiating activity on this interface.

The following table shows the AXI5 master interface signals. For more information about the AMBA® AXI5 signals, see the Arm® AMBA® AXI and ACE Protocol Specification.

Table A-4 MSC AXI5 master interface signals

Signal Direction Description
AW channel signals:
awvalid_m Output Write address valid signal.
awaddr_m[ADDR_WIDTH−1:0] Output Write address signal.
awburst_m[1:0] Output Write burst type signal.
awid_m[ID_WIDTH−1:0] Output Write request ID signal.
awlen_m[7:0] Output Write burst length signal.
awsize_m[2:0] Output Write burst size signal.
awlock_m Output Write lock type signal.
awprot_m[2:0] Output Write protection type signal.
awready_m Input Write address ready signal.
awcache_m[3:0] Output Indicates how transactions are required to progress through a system.
awregion_m[3:0] Output Permits a single physical interface on a slave to be used for multiple logical interfaces.
awqos_m[3:0] Output QoS identifier.
awuser_m[AWUSER_WIDTH−1:0] Output Write address channel User signals.
AR channel signals:
arvalid_m Output Read address valid signal.
araddr_m[ADDR_WIDTH−1:0] Output Read address signal.
arburst_m[1:0] Output Read burst type signal.
arid_m[ID_WIDTH−1:0] Output Read request ID signal.
arlen_m[7:0] Output Read address burst length signal.
arsize_m[2:0] Output Read burst size signal.
arlock_m Output Read lock type signal.
arprot_m[2:0] Output Read protection type signal.
arready_m Input Read address ready signal.
arcache_m[3:0] Output Indicates how transactions are required to progress through a system.
arregion_m[3:0] Output Permits a single physical interface on a slave to be used for multiple logical interfaces.
arqos_m[3:0] Output QoS identifier.
aruser_m[ARUSER_WIDTH−1:0] Output Read address channel User signals.
W channel signals:
wvalid_m Output Write data valid signal.
wlast_m Output Indicates last transfer in a write burst.
wstrb_m[(DATA_WIDTH/8)−1:0] Output Write byte lane strobes.
wdata_m[DATA_WIDTH−1:0] Output Write data signal.
wpoison_m[(DATA_WIDTH−1)/64:0] Output 64-bit data granule corruption indicator.
wuser_m[WUSER_WIDTH−1:0] Output Write channel User signals.
wready_m Input Write data ready signal.
R channel signals:
rvalid_m Input Read data valid signal.
rid_m[ID_WIDTH−1:0] Input Read data ID.
rlast_m Input Indicates last transfer in read data.
rdata_m[DATA_WIDTH−1:0] Input Read data.
rpoison_m[(DATA_WIDTH−1)/64:0] Input 64-bit data granule corruption indicator.
ruser_m[RUSER_WIDTH−1:0] Input Read channel User signals.
rresp_m[1:0] Input Read data response.
rready_m Output Read data ready signal.
B channel signals:
bvalid_m Input Write response valid signal.
bid_m[ID_WIDTH−1:0] Input Write response ID signal.
bresp_m[1:0] Input Write response signal.
buser_m[BUSER_WIDTH−1:0] Input Write response User signal.
bready_m Output Write response ready signal.

The following table lists the sideband signals on the AXI5 master interface.

Table A-5 MSC AXI5 master interface sideband signals

Signal Direction Description
awakeup_m Output When this signal is HIGH, it indicates that the MSC is initiating activity on this interface.

The following table lists the IDAU-Lite interface.

Table A-6 IDAU-Lite interface signals

Signal Direction Description
idau_awaddr[31:12] Output Write address.
idau_awns Input Non-secure indicator for write address.
idau_awunchk Input Uncheck indicator for write address.
idau_araddr[31:12] Output Read address.
idau_arns Input Non-secure indicator for read address.
idau_arunchk Input Uncheck indicator for read address.

The following table lists the interrupt signals.

Table A-7 MSC interrupt signals

Signal Direction Description
irq Output

When HIGH, it indicates a security violation or a faulty attribute conversion.

If the MSC sets irq HIGH, then the signal remains HIGH until the irq_clear signal is set HIGH for at least one clk cycle.

irq_clear Input This signal clears the interrupt, irq, assertion.

Note:

irq_clear has priority over interrupt generation, so when irq_clear is HIGH then no interrupts are generated. Therefore, you might miss a security event while irq_clear is HIGH.
irq_enable_rd Input

A debugger can use this signal to prevent interrupt generation for AXI read transactions:

0 = For read transactions, disable the generation of interrupts for security violations and faulty attribute conversions.

1 = For read transactions, enable the generation of interrupts for security violations and faulty attribute conversions.

irq_enable_wr Input

A debugger can use this signal to prevent interrupt generation for AXI write transactions:

0 = For write transactions, disable the generation of interrupts for security violations and faulty attribute conversions.

1 = For write transactions, enable the generation of interrupts for security violations and faulty attribute conversions.

The following table lists the configuration signals.

Table A-8 MSC configuration signals

Signal Direction Description
cfg_nonsec Input

Indicates the Security state of the AXI master that connects to the MSC. When cfg_nonsec is:

0 = AXI master is in the Secure state.

1 = AXI master is in the Non-secure state.

You can change the value of the configuration inputs during operation. The MSC samples the configuration inputs during the first clock cycle of an incoming transaction, when arvalid_s or awvalid_s is HIGH.

cfg_sec_resp Input

Controls how the MSC responds when it detects a security violation. When cfg_sec_resp is:

0 = MSC behaves as RAZ/WI, that is, reads return zero and it ignores writes.

1 = MSC responds with an ERROR response.

You can change the value of the configuration inputs during operation. The MSC samples the configuration inputs during the first clock cycle of an incoming transaction, when arvalid_s or awvalid_s is HIGH.

The following table lists the Q-Channel device signals.

Table A-9 Q-Channel signals for the MSC

Signal Direction Description
Clock control Q-Channel device signals:
clk_qreqn Input This signal indicates when the controller issues a quiescence entry or exit request to the MSC.
clk_qacceptn Output This signal indicates when the MSC accepts the quiescence request.
clk_qdeny Output This signal indicates when the MSC denies the quiescence request.
clk_qactive Output This signal indicates when the MSC is active and also when it requests to exit from quiescence.
Power control Q-Channel device signals:
pwr_qreqn Input This signal indicates when the controller issues a quiescence entry or exit request to the MSC.
pwr_qacceptn Output This signal indicates when the MSC accepts the quiescence request.
pwr_qdeny Output This signal indicates when the MSC denies the quiescence request.
pwr_qactive Output This signal indicates when the MSC is active and also when it requests to exit from quiescence.
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