Arm® CoreLink™ AHB Cache Technical Reference Manual

Revision r0p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback
Feedback on this product
Feedback on content
1 Overview
1.1 Basic terms
1.2 About the AHB Cache
1.3 Configurable features
1.4 Compatibility
1.5 Implementations
1.6 Compliance
1.7 Product documentation
1.8 Product revisions
2 Interfaces
2.1 Clocking and reset
2.2 AHB interface
2.2.1 Latency on the AHB interface
2.2.2 Write-Through and Write-Back support
2.2.3 Exclusive access sequences
2.2.4 Locked accesses and locked sequences
2.2.5 Error responses
2.2.6 XOM
2.2.7 Debug accesses
2.3 APB interface
2.4 Interrupts
2.5 Low-Power Interface
2.5.1 Dirty status indicator
2.5.2 Clock LPI
2.5.3 Power LPI
2.5.4 Quiescent state
3 Operation
3.1 Basic operations
3.1.1 Cache enable
3.1.2 Cache disable
3.1.3 Lookup
3.1.4 Linefill
3.1.5 Eviction
3.2 Performance monitoring
3.2.1 Snapshotting
3.3 Maintenance
3.3.1 Clean by address maintenance
3.3.2 Clean all maintenance
3.3.3 Invalidate by address maintenance
3.3.4 Invalidate all maintenance
3.3.5 Clean and invalidate by address maintenance
3.3.6 Clean and invalidate all maintenance
3.3.7 Automatic maintenance features
3.3.8 Manual maintenance
3.3.9 power_on_enable
4 Programmers model
4.1 About the programmers model
4.2 Programming considerations
4.3 Register summary
4.4 Register descriptions
4.4.1 HWPARAMS, hardware parameter register
4.4.2 CTRL, control register
4.4.3 NSEC_ACCESS, Non-secure access information register
4.4.4 MAINT_CTRL_ALL, maintenance control for the entire cache register
4.4.5 MAINT_CTRL_LINES, maintenance control for individual lines register
4.4.6 MAINT_STATUS, maintenance status for the cache register
4.4.7 SECIRQSTAT, Secure interrupt request status register
4.4.8 SECIRQSCLR, Secure interrupt status clear register
4.4.9 SECIRQEN, Secure interrupt enable register
4.4.10 SECIRQINFO1, Secure transfer error information register 1
4.4.11 SECIRQINFO2, Secure transfer error information register 2
4.4.12 NSECIRQSTAT, Non-secure interrupt request status register
4.4.13 NSECIRQSCLR, Non-secure interrupt status clear register
4.4.14 NSECIRQEN, Non-secure interrupt enable register
4.4.15 NSECIRQINFO1, Non-secure transfer error information register 1
4.4.16 NSECIRQINFO2, Non-secure transfer error information register 2
4.4.17 SECHIT, Secure transfers hit register
4.4.18 SECMISS, Secure transfers miss register
4.4.19 SECSTATCTRL, Secure transfers statistic counters control
4.4.20 NSECHIT, Non-secure transfers hit register
4.4.21 NSECMISS, Non-secure transfers miss register
4.4.22 NSECSTATCTRL, Non-secure transfers statistic counters control register
4.4.23 PMSVR0, saved value register 0 - Secure hit
4.4.24 PMSVR1, saved value register 1 - Secure miss
4.4.25 PMSVR2, saved value register 2 - Non-secure hit
4.4.26 PMSVR3, saved value register 3 - Non-secure miss
4.4.27 PMSSSR, PMU snapshot status register
4.4.28 PMSSCR, PMU snapshot capture register
4.4.29 PMSSRR, PMU snapshot reset register
4.4.30 PIDR4, peripheral ID register 4
4.4.31 PIDR5, peripheral ID register 5
4.4.32 PIDR6, peripheral ID register 6
4.4.33 PIDR7, peripheral ID register 7
4.4.34 PIDR0, peripheral ID register 0
4.4.35 PIDR1, peripheral ID register 1
4.4.36 PIDR2, peripheral ID register 2
4.4.37 PIDR3, peripheral ID register 3
4.4.38 CIDR0, component ID register 0
4.4.39 CIDR1, component ID register 1
4.4.40 CIDR2, component ID register 2
4.4.41 CIDR3, component ID register 3
A Signal descriptions
A.1 Clock and reset signals
A.2 LPI signals
A.3 AHB Slave interface signals
A.4 AHB Master interface signals
A.5 APB interface signals
A.6 System interface signals
A.7 Memory interface signals
A.7.1 Data RAM interface signals
A.7.2 Tag RAM interface signals
A.7.3 Dirty RAM interface signals
A.8 Configuration input ports
B Revisions
B.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-01 13 December 2019 Confidential First beta release for r0p0.
0000-02 24 April 2020 Non-Confidential First early access release for r0p0.

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