Appendix A. Revisions

This appendix describes the technical changes from Issue E and Issue F of this book.

Table A.1. Differences between Issue F and Issue G


Table A.2. Differences between Issue E and Issue F

TermChange
A32 instruction, was ARM instructionUpdated
A32 stateAdded
A64 instruction, was A64Updated
AArch32 state, was AArch32Updated
AArch64 state, was AArch64 stateUpdated
Abort modelUpdated
ACE interfaceAdded
ACE protocolAdded
ACE-Lite interfaceAdded
Advanced SIMDUpdated
APBUpdated
ARM instructionUpdated
ARM stateUpdated
ARM TrustZone® technologyUpdated
ATBUpdated
ATB bridgeUpdated
Automatic Test Pattern Generation (ATPG) [a]Removed
Authentication Asynchronous BridgeAdded
Authentication Synchronous BridgeAdded
Banked registersUpdated
Base registerUpdated
BounceUpdated
ClusterAdded
Coherence Order, CoherentAdded
Cold resetUpdated
CONSTRAINED UNPREDICTABLEAdded
Condition code checkAdded
Condition flagsUpdated
Conditional executionUpdated
Context synchronization operationUpdated
Context switchUpdated
CoprocessorUpdated
CoreAdded
Core registerUpdated
Cross-path blockingAdded
Current Program Status Register (CPSR)Updated
Data AbortUpdated
Data Timing Module (DTM) [a]Removed
Daughterboard Configuration ControllerAdded
Debug Communications Channel (DCC)Updated
Direct readAdded
Direct writeAdded
EndiannessUpdated
Exception Link Register (ELR)Added
Exceptional stateUpdated
Explicit accessUpdated
Fast Context Switch Extension (FCSE)Updated
Fixed-function pipelineRemoved
Fragment Thread CreatorAdded
G-POPRemoved
Generic Thread CreatorAdded
Granular Power RequesterAdded
Graphics Processor Unit (GPU)Removed
Half-rate clockingRemoved
Halting debug, was Halting debug-modeUpdated
Head-of-line blockingAdded
Hierarchical Tiler (HT)Added
High registersUpdated
High vectorsUpdated
Hit-Under-Miss (HUM)Updated
HTAdded
IEEE 1149.1 [a]Removed
IGNOREDAdded
IMPLEMENTATION SPECIFICUpdated
Imprecise tracingUpdated
In-Circuit EmulatorUpdated
Indirect readAdded
Indirect writeAdded
Instruction AbortAdded
Instruction Synchronization Barrier (ISB)Updated
Instrumentation traceUpdated
InterworkingUpdated
ISSMAdded
IT blockUpdated
Jazelle Extension, was Jazelle architectureUpdated
Jazelle DBXUpdated
Jazelle RCT (Runtime Compilation Target)Updated
Jazelle stateUpdated
Job system back-endUpdated
Link Register (LR)Added
Low-Power Interface (LPI)Added
Memory coherencyUpdated
Memory Management Unit (MMU)Updated
Memory Protection Unit (MPU)Updated
Monitor debug, was Monitor debug-modeUpdated
Motherboard Configuration Controller (MCC)Added
NEON technology, was NEONUpdated
Normal and Secure WorldsUpdated
OpenGL ES Shading Language (ESLL) [a]Removed
PLIAdded
Powerup resetAdded
Prefetch AbortUpdated
Processing Element (PE)Added
ProcessorAdded
PSTATEAdded
Quality of Service using Virtual Networks (QVN)Added
QVNAdded
RAZ/WIUpdated
Read-Only Position Independent (ROPI)Updated
Read Write Position Independent (RWPI)Updated
Register sliceAdded
RES0Added
RES1Added
ReservedAdded
RM, was Round towards Minus infinity (RM) modeUpdated
RN, was Round to Nearest (RN) modeUpdated
Rounding modeUpdated
RP, was Round towards Plus infinity (RP) modeUpdated
RZ, was Round towards Zero (RZ) modeUpdated
Saved Program Status Register (SPSR)Updated
SectionUpdated
Secure monitorUpdated
Security holeUpdated
Serial Configuration Controller (SCC)Added
Serial Power Controller (SPC)Added
Serial Wire or JTAG - Debug Port (SWJ-DP)Added
Should-Be-One-or-Preserved (SBOP)Updated
Should-Be-Zero-or-Preserved (SBZP)Updated
Single Instruction, Multiple Data (SIMD)Updated
SPCAdded
SPICERemoved
Stack Pointer (SP)Updated
Strongly-Ordered MemoryAdded
Subnormal valueUpdated
T32 instruction, was Thumb instructionUpdated
T32 state, was Thumb stateUpdated
T32EE instruction, was ThumbEE instructionUpdated
T32EE state, was ThumbEE stateUpdated
Test Access Port (TAP)Updated
Thin Links (TLX)Added
Tile bufferUpdated
Translation tableUpdated
Trap enable bitsUpdated
Trigger instructionUpdated
Trigger InterfaceAdded
Unified Assembler Language (UAL)Updated
UNKNOWNUpdated
UNPREDICTABLEUpdated
VectorizationUpdated
VFPUpdated
Write completionUpdated
Write interleave capabilityUpdated
XVC Test Scenario Manager (XTSM)Updated

[a] In general, the glossary does not define industry-standard terms unless the use of the term in ARM documents differs in some way from the usual understanding of the term.


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