Fast Models Portfolio 8.0 Release Notes
(version 8.0:47 dated 2012/12/07 17:48:38 GMT)

Introduction

Detailed documentation can be found in the 'doc' subfolder for Fast Models Tools and the 'Docs' subfolder for the Fast Models Portfolio.

A significant number of the examples in the Fast Models Portfolio 8.0 make use of images containing 3rd-party IP. These have been split out into a separate 'Third Party IP' package that can be downloaded from:

http://connect.arm.com
http://silver.arm.com

Not installing these images will mean that any examples that require dhrystone or the Linux images will not be functional, as well as any example using OSCI System C 2.2 and TLM 2.0.

Enhancements and changes in the Fast Models Portfolio 8.0 release

Fast Models 8.0 includes the following enhancements/changes since 7.1:

ARM AEMv8

Fast Models now adds support for the 64 bit Architecture Envelope Model, AEMv8. The following variants are introduced in the Fast Models 8.0 release, each with supporting peripherals:

- ARMAEMv8AMPCT - configurable MPCore processor.
- ARMAEMv8AMPx1CT - 1-core MPCore processor.
- ARMAEMv8AMPx4CT - 4-core MPCore processor.
- ARMAEMv8AUPCT - configurable UPCore processor.

Overview

The processors in these models are based on ARMv8 architectural specifications. The ARMv8 architecture is an extension to the ARMv7 architecture. The ARMv8 architecture extends the existing 32-bit architecture by introducing two execution states, the 32-bit AArch32 and the 64-bit AArch64.

Cache/TLB visibility

Visibility of cache and TLB components in A5, A7 and A15 models.

To enable cache and TLB CADI targets, the following environment variables should be set:

ARM Cortex-A15:
FM_EXPOSE_A15_TLB_CADI=1
FM_EXPOSE_A15_CACHE_CADI=1

ARM Cortex-A7:
FM_EXPOSE_A7_TLB_CADI=1
FM_EXPOSE_A7_CACHE_CADI=1

ARM Cortex-A5:
FM_EXPOSE_A5_TLB_CADI=1
FM_EXPOSE_A5_CACHE_CADI=1

To use cache CADI, the underlying cache model should be enabled by setting the following model parameters:

l1_icache-state_modelled
l1_dcache-state_modelled
l2_cache-state_modelled

Currently, searching by index is the only supported way to see the cache and TLB contents. This is done by setting the CACHE_SEL and TLB_SEL registers. Also the cache and TLB components should be selected when starting the model from the ModelDebugger.

New CoreLink400 controllers

Added support for the following CoreLink controllers:

- DMC-400 - Dynamic Memory Controllers
- TZC-380 - TrustZone Address Space Controller

SystemC enhancements

Slave DMI support

- AMBAPV2PVBus and AMBAPVACE2PVBus.
- get_direct_mem_ptr() is now supported.
- is_dmi_allowed() is now supported.

Limitations

- get_direct_mem_ptr(): FM will only return one naturally aligned 4k page per DMI request.
- get_direct_mem_ptr(): FM cannot return DMI access for any subrange of a 4k page. FM will always completely (READ_WRITE) deny DMI access for partially covered 4k pages.
- get_direct_mem_ptr(): DMI read/write latency gets lost (always 0 in response).
- PVBus2AMBAPV(ACE): invalidate_direct_mem_ptr(): FM propagates invalidate_direct_mem_ptr() only for 4k pages for which DMI has previously been requested (and granted or not granted) by any master, not for every 4k page in the address range given in the original invalidate_direct_mem_ptr().
- invalidate_direct_mem_ptr(): FM will call invalidate_direct_mem_ptr() once or twice per 4k page.
- invalidate_direct_mem_ptr(): FM may invalidate 4k pages also for pages for which DMI has been previously rejected.
- all TLM slaves which support DMI must call invalidate_direct_mem_ptr() when their memory content changes.

Global counter

It is now possible to export a Memory Mapped Counter module as a SystemC component.

ARM Cortex-A7 example

The following variants of ARM Cortex-A7 examples are included:
- ARM Cortex-A7x1
- ARM Cortex-A7x2
- ARM Cortex-A7x4

CADIIPC remote connection

Stability and performance improvements when connecting to models using the CADI interface.
- It is now possible to connect to models running on a remote machine.

CADI Client Integration Kit

The CADI Client Integration Kit (CCIK) is now shipped as standard with the Fast Models package. CCIK installation is not selected by default. The user should select the option during installation.

64 bit host model support for v5 and v6 architecture cores

64 bit host models for ARM926CT, ARM1136CT and ARM1176CT are supported.

Memory subsystem enhancements

The memory subsystem on Cortex R4 no longer generates spurious transactions to fetch instructions.

Deprecated in the Fast Models Portfolio 8.0 release

SystemC single instance will be removed from the next release of Fast Models.

Removed from the Fast Models Portfolio 8.0 release

Microsoft Visual Studio 2005 support has been removed.

CADI1.1 support has been removed.

Platform requirements for Microsoft Windows

When running Microsoft Windows XP or Microsoft Windows 7 it is recommended to use machines with at least 2GB RAM, and preferably at least 4GB for best performance. To use audio a 2GHz, or faster, Intel Core2Duo, or similar performing, processor is recommended.

Operating system: Microsoft Windows XP 32 Bit SP2 or SP3. Microsoft Windows 7 32 bit RTM or SP1, Professional or Enterprise editions. Microsoft Windows 7 64 bit RTM or SP1, Professional or Enterprise editions.

Compiler: Microsoft Visual Studio 2008 with Service Pack 1 and the Microsoft Visual Studio 2008 Service Pack 1 ATL Security Update. Microsoft Visual Studio 2010 with Service Pack 1.

Runtime Libraries: Fast Models Portfolio does not contain the Microsoft Visual Studio 2008 SP1 or Microsoft Visual Studio 2010 SP1 runtime libraries.

The Fast Models tools require the Microsoft Visual Studio 2008 SP1 runtime libraries to be installed. These must be downloaded from Microsoft.

Models built with Microsoft Visual Studio 2008 SP1 or Microsoft Visual Studio 2010 SP1 require the Microsoft Visual Studio 2008/2010 SP1 Redistributable Package to be installed in order to run.

64-bit host model support: In order to build 64-bit host models on Microsoft Windows, a host platform with a 64-bit CPU and a 64-bit version of Microsoft Windows is required, note that Microsoft Windows XP 64 is not supported. Microsoft Visual Studio 2008 SP1 and the Microsoft Visual Studio 2008 Service Pack 1 ATL Security Update or Microsoft Visual Studio 2010 SP1 is required.

Additional project configurations are available for most recently created System Canvas projects and selected updated example projects. To build for a Microsoft Windows host choose either 'Win64-Debug-VC2008', 'Win64-Release-VC2008', 'Win64-Debug-VC2010', or 'Win64-Release-VC2010'.

Please e-mail support-esl@arm.com with any comments.

To view the documentation, Adobe Acrobat or Reader needs to be installed on the system.

Platform requirements for Linux

When running on Linux it is recommended to use machines with at least 2GB RAM, and preferably at least 4GB for best performance. To use audio a 2GHz, or faster, Intel Core2Duo, or similar performing, processor is recommended.

Operating system: Red Hat Enterprise Linux 4 (on either 32 or 64 bit architecture) Red Hat Enterprise Linux 5 (on either 32 or 64 bit architecture) Red Hat Enterprise Linux 6 (on either 32 or 64 bit architecture)

Compiler:

When building models for 32bit hosts, Fast Models 8.0 for Linux supports the following compilers:
- gcc 4.1.2 (built against at least binutils 2.17)
- gcc 4.4.4

When building models for 64bit hosts, Fast Models 8.0 for Linux supports the following compilers:
- gcc 4.1.2 (built against at least binutils 2.17)
- gcc 4.4.4

64-bit host model support: In order to build 64-bit host models on Linux a host platform with a 64-bit CPU and a 64 bit version of RedHat Enterprise Linux version 4 or above is required. GCC 4.1.2 or upwards is required.

Additional project configurations are available for most recently created System Canvas projects and selected updated example projects. To build for a Linux 64-bit host, start System Canvas and change the 'Active Project Configuration' to one of the 'Linux64-Release-GCC' configurations, then rebuild the project.

To view the documentation, Adobe Acrobat or Reader needs to be installed on the system.

License management utilities

If you are using floating licenses, you must use FLEXnet license management utilities version 9.2 or higher. FLEXnet 10.8 license management utilities are available as an optional installable component in the product installer.

Use the highest version of the license management utilities provided with any ARM tools you are using. It is recommended to setup the user environment running applications of the Fast Models product only for one armlmd license server, because spreading Fast Models license features over different servers could result in license denials for certain features.

For more instructions on installing licenses please consult the ARM online documentation:

Installation notes

Microsoft Windows XP and Microsoft Windows 7

The Fast Models Portfolio installs its examples into the specified install location, which is normally under C:\Program Files\ARM\. On Microsoft Windows 7, without Administrative privilege, it is not possible to build and run the examples in situ. It is therefore necessary to copy the file hierarchy under C:\Program Files\ARM\FastModelPortfolio_8.0\examples to a local directory to which the user has read/write permissions. Once this is done, it is necessary to load examples into the System Canvas tool from this new location. (TA-588366/SDDKW-3784)

By default Microsoft Windows 7 does not provide an executable telnet client. For instructions on how to deal with this, please see the Fast Models Reference Manual section 5.

Linux

Once you have installed the Fast Models package, it is necessary to source the following script (dependent on shell) to setup up the appropriate environment variables. This should ideally be included such that it is sourced into the user's environment when they log in. bash/sh: . <install_directory>/FastModelTools_8.0/source_all.sh csh: source <install_directory>/FastModelTools_8.0/source_all.csh

TPIP

The Third-Party IP package (TPIP) must be installed after the Fast Models package.

Using the MPS platform model

Loading and running the platform

The platform model comes with a pre-built flash image that contains a slightly modified version of the MPS BootMonitor and the MPS SelfTests. The platform has a parameter for the name of the file that is loaded into the flash on startup. In order to use the flash image this parameter needs to be set properly:

Examples: with a relative path: coretile.fname=mps_flash.bin with an absolute path on Microsoft Windows assuming the default installation directory: coretile.fname="C:\Program Files\ARM\FastModelPortfolio_8.0\examples\RTSM_MPS\mps_flash.bin" with an absolute path on Linux assuming the default installation directory: coretile.fname="/home/username/ARM/FastModelPortfolio_8.0/examples/RTSM_MPS/mps_flash.bin"

The BootMonitor can be used to start images from flash.
- To enter the flash menu type "flash"
- To list the available images then type "list images"
- To run an image type e.g. "run selftest_mpb_ESL"

When running the MPS SelfTests, the following tests are expected to fail on the MPS platform model:
- 1.1 Audio Loopback Reason: no loopback simulated
- 10 USB Reason: USB not supported

Using the ARM Profiler with Fast Models 8.0

Fast Models version 8.0 supports ARM Profiler version 2.1, as shipped in ARM RealView Development Studio 4.0 SP2, and later. It does not support the use of ARM Profiler 2.0 or earlier, which was shipped in ARM RealView Development Studio 4.0 and 4.0 SP1.

If you currently have ARM Profiler 2.0 and wish to use the ARM Profiler with Fast Models 8.0, it will be necessary to upgrade to ARM RVDS 4.0 SP2. Please contact ARM support for further details.

Using TAP/TUN-based model networking

Fast Models version 6.0 added a new model-to-host networking implementation based on TAP/TUN. This has a number of advantages compared to the previous version:
- Only requires root / administrator access at install time.
- No longer requires nicserver.

Installation instructions for Model Networking can be found in the Fast Models Reference Manual, sections 5.4.45, 5.6.3, and 5.6.4.

However, due to the different implementation and configuration methods, you may encounter some issues during installation:

1. Symptom: The model networking worked after the first time setup, then stop working after reboot.

Solution: This is typically caused by /dev/net/tun not having correct access permissions. To fix this, set the correct permission to the device by executing "chmod 666 /dev/net/tun" as root. To preserve the change across reboots, the udev rules of the tap device need to be modified:

Open /etc/udev/rules.d/50-udev.rules as root, find the line KERNEL=="tun", NAME="net/%k"

Check if it has MODE="0666" at the end of the line. If not, append MODE="0666" to the line:

KERNEL=="tun", NAME="net/%k", MODE="0666"

2. Symptom: Model Networking installs correctly, however when a model is started, the model cannot receive any packets.

Solution: This is typically caused by the firewall on the host machine. Disable the firewall, or add tap device to "trusted devices". Please refer to your vendor's documentation manual for how to do this.

Outstanding issues

CT models

- The Fast Models will not hit in any cache when the cache is disabled even if a cores TRM state the hardware will. (SDDKW-20563)

- DMA into TCMs can produce incorrect results in big endian mode. (TA-506423/SDDKW-2770)

- Connecting to multiple RTSM or Model Library models concurrently using RealView Debugger can cause instability. This applies to all models which have been generated using Fast Models. (TA-514865/SDDKW-2895)

- Exception breakpoints appear in Model Debugger's breakpoint manager, however they cannot be configured. This can be worked around by configuring them using the "Exception Traps" register pane instead. (TA-550165/SDDKW-3193)

- The Cortex-R4 fast model treats TCM memory as cacheable. If both TCMs and caches are configured and the TCM memory is marked cacheable then the model will respect this and pollute the cache. In the real device TCM memory is never cacheable even if marked as such. (SDDKW-3206)

- The Cortex-A9MP and Cortex-A5MP fast models ignore the SCU invalidate all register. (TA-558715/SDDKW-3385)

- The Cortex-A9MP and Cortex-A5MP fast models ignore the SCU enable bit. Therefore the SCU is always enabled. (TA-558221/SDDKW-3373)

- The Cortex-A9MP and Cortex-A5MP fast models do not implement address filtering within the SCU. The enable bit for this feature is ignored. (TA-558719/SDDKW-3388)

- Functional caches are architectural cache models that do not have device accurate behavior relating to tag allocation, victim selection and physical/virtual indexing behavior. (TA-732864/SDDKW-8185)

- Broadcast Translation Lookaside Buffer(TLB) or cache operations in the Cortex-A9MP fast model do not cause other cores in the cluster which are asleep due to Wait For Interrupt(WFI) to wake up. (TA-558220/SDDKW-3372)

- The Cortex-R4 fast model ignores the Cache Size Override register. (TA-572916/SDDKW-3584)

- vfp registers are not displayed if 'ase-present' is set. Enabling the 'ase-present' parameter should force the 'vfp-present' parameter to be set automatically. This is not currently implemented so it is necessary to manually set 'vfp-present' when setting 'ase-present'. This will then enable the display of vfp registers. (TA-571230/SDDKW-3554)

- Cortex A8 L2 cache write allocate policy is not configurable. It defaults to write-allocate. Writes to the configuration register will succeed but will be ignored, meaning that data can be unexpectedly stored in the L2 cache. (TA-573071/SDDKW-3598)

- Default PVBus bus response for exclusive access has the wrong sense. EXOK should be mapped to TX_OK and OK should be mapped to TX_EXCLUSIVEABORT for exclusive access. TLM2 AMBA-PV behaves correctly. (TA-641720/SDDKW-4491)

- When taking an exclusive read abort the Cortex-A9 model can return an fsr with a value of 0, which is not valid. (TA-639621/SDDKW-4446)

- PVBus function getMasterID() may be deprecated in a future release. (TA-659219/SDDKW-4677)

- Models only support some types of memory breakpoints. Currently the error message returned if an unsupported type is used may not clearly indicate that the breakpoint type is unsupported. (TA-662969/SDDKW-4722)

- pv::TransactionGenerator does not support exclusive accesses. (TA-659218/SDDKW-4676)

- CADI calls not supported by Fast Models. The following methods are not supported by Fast Models:

CADI: Parameter API CADIGetParameters() CADIGetParameterInfo() CADIGetParameterValues() CADISetParameters() Register API CADIGetCommitedPCs() Memory API CADIMemGetOverlays() Virtual Memory API VirtualToPhysical() PhysicalToVirtual() Cache API CADIGetCacheInfo() CADICacheRead() CADICacheWrite() Execution API CADIExecLoadApplication() CADIExecUnloadApplication() CADIExecGetLoadedApplications() CADIExecAssertException() CADIExecGetPipeStages() CADIExecGetPipeStageFields() CADIGetCycleCount()

CADIDisassembler: GetSourceReferenceForAddress() GetAddressForSourceReference() GetInstructionType()

CADIDisassemblerCB: ReceiveSourceReference()

CADIProfiler:

(TA-684124/SDDKW-5033)

- CADI methods deprecated for use in Fast Models 8.0:

CADICallbackObj appliOpen() appliClose() cycleTick() killInterface() (TA-684124/SDDKW-5033)

- The unused legacy CADI configuration parameter 'semihosting-debug' has been removed from all CoreTile models. (SDDKW-14777)

- Attempting to instantiate a system model with more than 200+ CADI objects may cause the simulation to crash when the CADI client is connected. (SDDKW-16447)

- "Goto Main" from Model Debugger is not supported with Cortex-A9MP, Cortex-A9UP, Cortex-A5MP and Cortex-A5UP fast models. (TA-571017/SDDKW-3550)

- The Cortex-A9MP and Cortex-A5MP GIC does not implement the cfgsdisable behaviour to make some registers read-only. (TA-549471/SDDKW-3190)

- FlashLoader now has parameters to allow the flash file to be saved at the end of a simulation, preserving flash contents as would happen on real hardware. This functionality is Beta quality and may not work in all cases. (TA-721877/SDDKW-6651)

- Cortex A8 does not support a zero-sized L2 cache. All other cache sizes are supported. (TA-725232/SDDKW-7393)

- When attempting to debug an ISIM system, if you launch Model Debugger from System Canvas and then specify an application to load this causes an error in Model Debugger (Error using application...), and the model and application fail to load.

Workaround: Launch Model Debugger without specifying an application, and then load the application from within Model Debugger itself using File -> Load Application Code. (SDDKW-10295)

- The GIC-400 model has the following limitations:
- Reads and writes to the GICD_ISACTIVERn/GICD_ICACTIVERn/GICD_ISPENDRn/GICD_ICPENDRn may not work as expected unless there is a configured target in GICD_ICFGRm.
- Some of the interaction of GICD_CTLR.EnableGrpX and level sensitive interrupts may not work entirely correctly.
- The signals nIRQOUT/nFIQOUT are not modelled.
- All interrupts are modelled with positive logic, rather than the negative logic used in the hardware. Hence all signal pins have their 'n' prefix dropped. (SDDKW-13075)

- The Cortex A15 and Cortex A7 models claim to have parameters named CFGNMFI, POWERCTLI, and SMPnAMP. These settings do not correspond to hardware functionality, and their value will be ignored by the model. (SDDKW-12392)

- The FastModels documentation states that a LISA component that is going to act as a bus slave must instantiate a PVBusSlave sub-component. There was a back door where a slave port of type PVBusProtocol could simply implement a read() and write() method without requiring a PVBusSlave sub-component. This was not intended usage, and as of FM7.0 this back-door no longer works. LISA component designers must now adhere to the instructions given in DUI0423 (see 5.2.5 PVBusSlave component) and/or copy the structure of the FastModels example peripherals. (SDDKW-13968)

- There is a limitation in the ACE cache models in Cortex-A15 and Cortex-A7, and the ACE support in the CCI-400: these functional models only handle processing a single transaction at a time. Under normal use this won't cause any problems, because the simulation will process each transaction to completion before allowing any master to generate another transaction.

There are two situations in which this might fail:

- 1) If there is a loop in the bus topology, such that there is a path of bus connections going out of the master port from a component back into one of its slave ports. This can potentially cause problems even if it isn't possible for a single transaction to go round the loop (for example, if there are bus-decoders that limit the paths that a transaction can take). (SDDKW-13039)

- 2) If a SystemC bus slave calls wait() while it is processing a transaction, it may allow another master to issue a transaction that passes through the CCI-400 or the Cortex-A15/Cortex-A7 caches. This could happen if a SystemC bus master running in another thread is connected to one of the ACE-lite ports on the CCI-400. (SDDKW-12826)

Contact ARM for further details if these restrictions are likely to cause problems.

- With cache state modelling enabled there is a limitation that WT transactions are not snooped upstream from the CCI. This does not caues any issues when the CCI is connected to the FastModels ARM cores that support ACE, the A15 and the A7, but could be an issue for a cache implemented in a System-C component that is upstream of the CCI and connected to a full ACE port on the CCI. (SDDKW-18832)

- When generating SystemC Export components on Windows, you might see warning messages such as:

"_WIN32_WINT: macro redefinition"

This is issued by an unguarded setting of _WINVER in the OSCI SystemC headers. Fast Models request a later version of the Win32 API elsewhere in its generated code causing this warning. This warning can be safely ignored. (SDDKW-13781, SDDKW-13523)

- RVD 4.0 cannot be used to step or run an A9 model. In order to do this, RVD 4.1, DS-5, or ModelDebugger is needed. (SDDKW-15171)

- The TelnetTerminal can only manage one active connection at a time. When there is an incoming connection, this is given priority and any existing connections are closed by the server. Previously, TelnetTerminal in versions of Fast Models up to 7.0 had ignored incoming connections where there was an existing connection. (SDDKW-8463)

- UCVTF could use the wrong rounding mode on 32bit hosts only. (SDDKW-19864)

- Use preferred behaviour for unpredictable case of LDRT using pc. (SDDKW-19716)

- Attempting to instantiate a system model with more than 200+ CADI objects may cause the simulation to crash when the CADI client is connected. (SDDKW-19603)

- VLDM with out-of-range register list should take UNDEFINED exception. (SDDKW-19572)

- Value of ID_AA64DFR0_EL1 and some other ID registers may be incorrect. (SDDKW-19566)

- Crypto and VFP instructions were not checking for unpredictable case in IT block. (SDDKW-19537)

- The checking for the unpredictable LSL of 0 bits was incorrectly applied to ASR, meaning the T1 encoding of ASR with immediate of #32 was being treated as unpredictable. (SDDKW-19445)

- Problems in the licensing code which caused the model to check out two licenses instead of one. (SDDKW-19414)

- When debug stepping over an IRQ, the syndrome in DBGDSCR can be incorrect ("halting step, no syndrome" instead of "halting step, normal"). (SDDKW-19404)

- For LDREXD with rt2 is pc, model now implements preferred behaviour (pc write is ignored). (SDDKW-19372)

- Model was not following ARM recommended unpredictable behaviour when SBZ bits in T1 CPS instruction were set. Now ignores those bits. (SDDKW-19357)

- VMRS pc, fpsid has incorrect unpredictable behaviour. (SDDKW-18893)

- UNPREDICTABLE use of R15 as base register for load/store does not match AArch32 standard behavior on ARMv8. (TA-534369/SDDKW-20471)

- simulation hangs due to the Fast Models SC_THREADs getting stuck in wait() when the FASTSIM_SLEEP_ON_WFIWFE option is enabled. (TA-534006/SDDKW-20342)

- Access to Vendor_SYS memory region (0xE0200004) in unprivileged mode does not fault on M4 Model. (TA-533691/SDDKW-20327)

- LDREX fails when going through AMBAPVACE bridge. (TA-531580/SDDKW-20078)

- The loczrama port of the Cortex-R5, although present, is not functional and therefore should not be connected. If driven the simulation will terminate. (TA-530060/SDDKW-19889)

- SystemC application is blocked when using dlopen/dlclose/dlopen sequence and trying to print message. (TA-528561/SDDKW-19739)

- Extended features register "PC_MEMSPACE" does not change value to reflect the execution mode(Normal/Secure). This problem is noticed on A-profile models. (TA-528114/SDDKW-19710)

- simulation freezes when stepping a core that is halted by setting the halt_core register. (TA-528092/SDDKW-19689)

- AMBA-PV should CleanUnique transaction have a data pointer. (TA-523825/SDDKW-19618)

- A15 produces illegal bus transactions. (TA-520481/SDDKW-19001)

- Cortex-A15 model sometimes crashes when getting out of Hypervisor mode. (TA-517772/SDDKW-17448)

- CADI and MTI names for CP15 registers are different. (TA-514407/SDDKW-16762)

- Reset value for MIR register in smsc_91c111 ethernet controller. is incorrect (TA-512419/SDDKW-16123)

- A15 does not emit MTI BUS_READ_ACCESS and BUS_WRITE_ACCESS events. (TA-523210/SDDKW-14090)

- MPCore does not abort when accessing abort-able regions of the private memory region. (TA-492286/SDDKW-12033)

Model Trace Interface (MTI)

- Trace output from the ARM Cortex-M3 fast model has the following known limitations:
- The xPSR register is currently called "CPSR" in the register trace events. (TA-723280/SDDKW-7025)

- Fast Models 6.1 introduced the ability to unregister an MTI callback whilst within the same callback. This does not work for adding new callbacks or unregistering any other callback and may result in a crash or unexpected extra calls to unrelated callbacks. (SDDKW-11567)

- The SRS instruction was reporting incorrect store transactions in TarmacTrace output. (SDDKW-18124)

- The source code for the LinuxSyscallTrace plugin, currently supplied as an MTI Plugin example, is faulty. This is because the code relies on a particular ordering of components within the model which in not guaranteed for any given platform model. This means that the plugin will fail to register properly on some FastModels example platforms. (SDDKW-18570)

- If a plugin is created and the MTI::PluginFactory::Instantiate() method returns a pointer to a location above the 4G address space then the simulation may segfault if the MTI trace callback is called. (SDDKW-12628)

CLCD

- SDL, the library used to provide the visualization component, can only open one window per process. Models should only ever open one window. (TA-455617/SDDKW-2246)

PL011 UART

- The following parameters of the PL011 UART are being deprecated in the next release of the product: clock_rate baud_rate uart_enable (TA-641768/SDDKW-4497)

Model generation

- If a PARAMETER has no type specified, PARAMETER will default to a uint32_t and a warning will be generated. It is recommended that type be specified explicitly as this warning may be promoted to an error in a future version. (SDDKW-7124)

Networking

- The default firewall configuration on Redhat Enterprise Linux 5 blocks transmission of packets across the bridge device created as part of the Fast Models TAP networking solution. This will lead to a loss of host network connectivity if TAP based networking is configured on a host with the firewall active. This can be worked around by disabling the firewall. If the models are to be used in an environment where it is not possible to disable the firewall then additional firewall rules will be required to allow transmission. The following iptables commands should configure the firewall to allow packets across the bridge device.

1) iptables -I FORWARD -m physdev --physdev-is-bridged -j ACCEPT 2) service iptables save 3) service iptables restart (SDDKW-14139)

- If Dynamic DNS is being used to by the host such that suitable records are inserted into DNS if the host is managed via DHCP installing TAP networking may cause failure to register in the DNS. This happens due to the DHCP client being rerun after the physical device is attached to the bridge device. At this point the correct hostname is not passed in the DHCP request. There is no workaround for this issue at this time. (SDDKW-14140)

- Most WiFi adaptors do not implement the required support for TAP networking to work. There is no workaround for this problem. (SDDKW-14142)

- In the technology preview of the User Mode Networking support the RFC1918 address space used was 172.31.254.0/24 this is the last subnet in the space and is not recommended it is chosen via an obvious rule and is more likely to conflict with RFC1918 space used in a users environment. This has been changed to the arbitrarily chosen 172.20.51.0/24. (SDDKW-14027)