Release notes for ARM Compiler toolchain v5.0u1

Enhancements in v5.0u1

Compiler (armcc)

• Performance optimized compiler support for Marvell PJ4. This is enabled with --cpu=PJ4 [SDCOMP-15525]
• The default behaviour has changed for using VFP registers for non-VFP data. The default is now --no_allow_fpreg_for_nonfpdata. To enable the use of VFP registers for non-VFP data, --allow_fpreg_for_nonfpdata can be used. [SDCOMP-14831]

Note: the change in the default behaviour may cause performance regression in some cases. However, it is possible to regain 5.0 performance level by specifying the --allow_fpreg_for_nonfpdata option.

• An option has been added to control the generation of conditionalized instructions.

  • --no_conditionalize will disable the generation of conditionalozed instructions
  • --conditionalize will allow the generation of conditionalized instructions

  The default behaviour is to emit conditionalized instructions based on the --cpu option.

  [SDCOMP-15107]
• Support for the ARM Secure Core SC000 processor has been added. This is enabled with --cpu=sc000 [SDCOMP-15550]

Format Converter (fromelf)

• A new option has been added to fromelf. --force_import takes a list of symbols and allows the conversion of each locally referenced symbol to a globally undefined symbol. For each symbol in the input list, --force_import :

  • Removes the symbol from the static symbol table.
  • Changes the dynamic symbol entry to have default visibility and be undefined with value 0.
  [SDCOMP-15339]

Linker (armlink)

• Two command line options have been added to give more control over the generation of BLX instructions. --no_blx_arm_thumb controls whether the linker can generate a BLX instruction for ARM to Thumb calls. --no_blx_thumb_arm controls whether the linker can generate a BLX instruction for Thumb to ARM calls. These options default to allowing BLX instructions to be generated. [SDCOMP-14942]

Corrections in v5.0u1

Assembler (armasm)

• Inline assembly containing PKHTB instructions without a shift (or with a shift of 0) were erroneously faulted with compiler error #2897. This is now corrected. [SDCOMP-13645]

Compiler (armcc)

• Using a pointer cast to reinterpret a signed short or char as an unsigned one, for example ss = (signed short)&us;, could fail to sign-extend the answer correctly when it was next widened to an int. [SDCOMP-13525]
• An instance of the incorrect use of __aeabi_memmove was seen when compiling with -O3. This has been corrected. [SDCOMP-13931]
• When returning a struct containing long long types from a function with value_in_regs in big endian mode, the long long members of the struct could have their words reversed. [SDCOMP-13968]
• Instances of internal fault 0x6f65fa, 0x3a34f4 have been corrected. [SDCOMP-13990], [SDCOMP-14738]
• When compiling large switch statements to Thumb code, if the variable used in the switch is used in or after the switch block, the compiler could use the incorrect value for this variable. This could happen at all optimization levels, and has been corrected. [SDCOMP-14100]
• If a variable which is assigned the result of an __ldrex or __ldrt intrinsic, is used in subsequent expressions which only read a portion of the variable, the compiler could incorrectly emit a read of the whole variable. [SDCOMP-14291]
• The compiler has been updated to generate correct code for bitbanded structs. This bug was only observable when compiling some test cases at -O0 optimization level. [SDCOMP-14636]
• 'Q' flag handling has been improved. [SDCOMP-14723]
• On ARM v7M and v7EM processors, LDRD/STRD instructions are not single-copy atomic. The compiler now generates two LDR/STR instructions to access a 64-bit volatile data for these processors. [SDCOMP-14821]
• When using vectorization, the compiler would sometimes generate an incorrect shift when combined with conditional execution. This has been corrected. [SDCOMP-14857]
• In rare circumstances, if the compiler generated an LDM or STM with writeback, it was possible that later loads or stores using the same base would have incorrect offsets. [SDCOMP-14880]
• When doing a signed 64-bit constant multiply, where the 64-bit constant is INT32_MAX > x <= UINT32_MAX, the compiler could generate incorrect code for this, giving incorrect results. [SDCOMP-14921]
• A defect has been fixed where the compiler would incorrectly transform code that performs a right-shift of a 64-bit value followed by a bitwise-and of certain literal values. [SDCOMP-15050]
• Warning: #68-D: integer conversion resulted in a change of sign was incorrectly generated in some cases. This has been corrected. [SDCOMP-15095]
• When compiling at -O3 -Otime --vectorize, the compiler could incorrectly unroll a vectorized loop, such that offsets of arrays would be incremented too many times. [SDCOMP-15105]
• A defect in the inline assembler that caused BKPT instructions to not be generated has been fixed. [SDCOMP-15171]
• The compiler could previously generate internal fault 0x8d2481 when compiling for Cortex-M processors and using Profile-Guided Optimization (--profile). This has been fixed. [SDCOMP-15216]
• At high optimization levels, when the option --no_allow_fpreg_for_nonfpdata is specified, the compiler could still generate NEON code for an unaligned memcpy of small sizes. [SDCOMP-15237]
• In certain circumstances, where an OR between two consecutive signed short or char array accesses is created, the compiler may incorrectly optimize this into one word/short array access, ignoring the effects of sign extension. [SDCOMP-15258]
• When inlining a function where the caller passes a non word aligned pointer as an argument, and the callee dereferences this pointer, the compiler could sometimes access the pointer with an incorrect offset. This has been corrected. [SDCOMP-15285]
• In very rare circumstances, in a function that uses a register but doesn't set it, so doesn't push it onto the stack (for example using an undefined value), later LDM/STM instructions generated could then corrupt this register. [SDCOMP-15294]
• Warning: #68-D: integer conversion resulted in a change of sign was incorrectly generated at higher optimisation levels. This incorrect warning generation will no longer happen. [SDCOMP-15366]
• In the previous patch, inline assembly containing PKHTB instructions without a shift (or with a shift of 0) was been erroneously faulted with compiler error #2897. This is now fixed. [SDCOMP-13645]
• When in GNU C99 mode, and emulating GCC 4.3+, the compiler will now generate an out of line copy for an extern inline function. [SDCOMP-14441]
• Internal fault 0x05ced5 was seen when using --remove_unneeded_entities. This has been corrected. [SDCOMP-15032]
• Warning: #152-D: conversion of nonzero integer to pointer was incorrectly reported at high optimisation levels. This has been corrected. [SDCOMP-15392]

Libraries

• The library symbol __fpl_infinity had default visibility. This should not be visible and is now hidden. [SDCOMP-15387]

Linker (armlink)

• The linker in all previous versions could suffer from relocation out of range problems. This was caused by the elimination of identical exception table entries, which altered the addresses that linker was using to calculate branch range. This has now been fixed. A side effect of the fix is that the placement of veneers within the execution region may change. If you are using the default "lexical" sorting algorithm there will be no change. If you are using an alternative sorting algorithm to "lexical", by using the --sort option, the linker will place the veneers after the RO-CODE in the execution region. [SDCOMP-13534]