Energy-efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-time SMT processor

Research paper

This paper focuses on the instruction fetch resources in a real-time SMT processor to provide an energy-e cient con guration for a soft real-time application running as a high priority thread as fast as possible while still o ering decent progress in low priority or non-realtime thread(s). We propose a fetch mechanism, Fetch-around, where a high priority thread accesses the L1 ICache, and low priority threads directly access the L2. This allows both the high and low priority threads to simultaneously fetch instructions, while preventing the low priority threads from thrashing the high priority thread's ICache data. Overall, we show an energy-performance metric that is 13% better than the next best policy when the high performance thread priority is 10x that of the low performance thread.

This document is only available in a PDF version.

Copyright © 2009 ARM Limited. All rights reserved. ARM ARP0013A
Non-Confidential