The Challenges of Correlating Silicon and Models in High Variability CMOS Processes

Research paper

This talk discusses one of the key challenges of post-silicon validation: namely, the difficulty inherent in correlating observed behavior with modeled behavior. Validation must account for a large number of sources of inherent variability in the silicon, ranging from those inherent in the device and wire models themselves through approximations made in library modeling, extraction, tool algorithms and so on. The problem is further complicated by defects and systematic errors that can be present in early silicon. In addition, environmental factors such as temperature and on-chip power supply must be understood, and lastly variation in the measurement equipment must also be correctly accounted for. Examples are given for validating standard cell and memory based designs as well as a general methodology that can be used to enable chip bring-up.

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