On all systems, it will be necessary to enable the VFP by
setting the VFPEnable bit in the VFP's FPEXC register. Until this
is done, the VFP coprocessor is disabled and any other access to
the VFP causes an undefined instruction exception. When reinitializing
the VFP it is also necessary to reset the EX bit in this register,
to clear any pending exceptions. This operation must be carried
out in a privileged mode.
Architecture V6 and later
Due to changes made in V6 and later architectures in the way
in which the VFP coprocessor interfaces with the core processor,
the VFP support code has some conditional actions which apply only
to architecture V6 or later (such as VFP11). Coprocessors CP10 and
CP11 must be enabled by setting bits 20-23 (b1111 gives full read/write
access) of the Coprocessor Access Control Register. For more information
please refer to the technical reference manual of the ARM processor
core that you are using.
VFPEnable EQU 0x40000000
GBLL ARCH_V6_OR_LATER ;Create global variable
IF "6" <= {ARCHITECTURE} ; ok until architecture 10
ARCH_V6_OR_LATER SETL {TRUE}
ELSE
ARCH_V6_OR_LATER SETL {FALSE}
ENDIF
Enable_VFP FUNCTION
IF ARCH_V6_OR_LATER
MRC p15, 0, r1, c1, c0, 2 ; r1 = Access Control Register
ORR r1, r1, #(0xf << 20) ; enable full access for p10,11
MCR p15, 0, r1, c1, c0, 2 ; Access Control Register = r1
MOV r1, #0
MCR p15, 0, r1, c7, c5, 4 ; flush prefetch buffer because of FMXR below
; and CP 10 & 11 were only just enabled
ENDIF
; Enable VFP itself
MOV r0,#VFPEnable
FMXR FPEXC, r0 ; FPEXC = r0
BX LR
ENDFUNC
PDF version 
All files